32.1 MPDDRC Mode Register

This register can only be written if the WPEN bit is cleared in the MPDDRC Write Protection Mode Register.

Name: MPDDRC_MR
Offset: 0x00
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
      MODE[2:0] 
Access R/WR/WR/W 
Reset 000 

Bits 2:0 – MODE[2:0] MPDDRC Command Mode

This field defines the command issued by the MPDDRC when the SDRAM device is accessed. This register is used to initialize the SDRAM device and to activate Deep Power-down mode.

ValueNameDescription
0NORMAL_CMDNormal Mode. Any access to the MPDDRC is decoded normally. To activate this mode, the command must be followed by a write to the DDR-SDRAM.
1NOP_CMDThe MPDDRC issues a NOP command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM.
2PRCGALL_CMDThe MPDDRC issues the All Banks Pre-charge command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM.
3LMR_CMDThe MPDDRC issues a Load Mode Register command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM.
4RFSH_CMDThe MPDDRC issues an Auto-refresh command when the DDR-SDRAM device is accessed regardless of the cycle. Previously, an All Banks Pre-charge command must be issued. To activate this mode, the command must be followed by a write to the DDR-SDRAM.
5EXT_LMR_CMDThe MPDDRC issues an Extended Load Mode Register command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. The write in the DDR-SDRAM must be done in the appropriate bank.
6DEEP_CMD

Deep Power mode: Access to Deep Power-down mode