32.2 MPDDRC Refresh Timer Register

This register can only be written if the WPEN bit is cleared in the MPDDRC Write Protection Mode Register.

Name:	MPDDRC_RTR
Offset:	0x04
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
					COUNT[11:8]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
	COUNT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 11:0 – COUNT[11:0] MPDDRC Refresh Timer Count

This 12-bit field is loaded into a timer which generates the refresh pulse. Each time the refresh pulse is generated, a refresh sequence is initiated.

The SDRAM requires auto-refresh cycles at an average periodic interval of T_refi. The value to be loaded depends on the MPDDRC clock frequency MCK (main system bus clock) and average periodic interval of T_refi.

For example, for an SDRAM with T_refi = 7.8 μs and a 133 MHz (7.5 ns) main system bus clock, the value of the COUNT field is configured: ((7.8 × 10^-6) / (7.5 × 10^-9)) = 1040 or 0x0410.