32.17 MPDDRC Read Data Path Register
| Name: | MPDDRC_RD_DATA_PATH |
| Offset: | 0x5C |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SHIFT_SAMPLING[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
Bits 1:0 – SHIFT_SAMPLING[1:0] Shift Sampling Point of Data
Shifts the sampling point of data coming from the memory device. The higher the memory device clock frequency, the higher the SHIFT_SAMPLING value. Refer to the section "Electrical Characteristics".
| Value | Name | Description |
|---|---|---|
| 0 | NO_SHIFT | Initial sampling point. |
| 1 | SHIFT_ONE_CYCLE | Sampling point is shifted by one cycle. |
| 2 | SHIFT_TWO_CYCLES | Sampling point is shifted by two cycles. |
| 3 | SHIFT_THREE_CYCLES | Sampling point is shifted by three cycles. Not applicable for DDR2 and LPDDR1 devices. |