32.23 MPDDRC Monitor Information Port x Register (TOTAL_LATENCY_QOS01)

Name: MPDDRC_MINFOx (TOTAL_LATENCY_QOS01)
Offset: 0x84 + x*0x04 [x=0..3]
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
 Px_TOTAL_LATENCY_QOS1[15:8] 
Access RRRRRRRR 
Reset 00000000 
Bit 2322212019181716 
 Px_TOTAL_LATENCY_QOS1[7:0] 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 Px_TOTAL_LATENCY_QOS0[15:8] 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 Px_TOTAL_LATENCY_QOS0[7:0] 
Access RRRRRRRR 
Reset 00000000 

Bits 31:16 – Px_TOTAL_LATENCY_QOS1[15:0] Total Latency on Port x when value of qos is 1

Can be read if the INFO field is set to 4.

Reports the total latency within an interval (ADDR_HIGH_PORT and ADDR_LOW_PORT) when the port is used with qos = 1.

Bits 15:0 – Px_TOTAL_LATENCY_QOS0[15:0] Total Latency on Port x when value of qos is 0

Can be read if the INFO field is set to 4.

Reports the total latency within an interval (ADDR_HIGH_PORT and ADDR_LOW_PORT) when the port is used with qos = 0.