32.6 MPDDRC Timing Parameter 2 Register
| Name: | MPDDRC_TPR2 |
| Offset: | 0x14 |
| Reset: | 0x00042062 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TFAW[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 1 | 0 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TRTP[2:0] | TRPA[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 1 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXARDS[3:0] | TXARD[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | |
Bits 19:16 – TFAW[3:0] Four Active Windows
DDR2 devices with eight banks (1 Gbit or larger) have an additional requirement concerning tFAW timing. This requires that no more than four Activate commands may be issued in any given tFAW (MIN) period.
The number of cycles is between 0 and 15.
Bits 14:12 – TRTP[2:0] Read to Precharge
Defines the delay between a Read command and a Precharge command in number of DDRCK clock cycles.
The number of cycles is between 0 and 7.
Bits 11:8 – TRPA[3:0] Row Precharge All Delay
Defines the delay between a Precharge All Banks command and another command in number of DDRCK clock cycles. The number of cycles is between 0 and 15.
This field is found only in the DDR2-SDRAM devices.
Bits 7:4 – TXARDS[3:0] Exit Active Power Down Delay to Read Command in Mode “Slow Exit”
Defines the delay between CKE set high and a Read command in number of DDRCK clock cycles. The number of cycles is between 0 and 15.
This field is found only in the DDR2-SDRAM devices.
Bits 3:0 – TXARD[3:0] Exit Active Power Down Delay to Read Command in Mode “Fast Exit”
This field is found only in the DDR2-SDRAM devices.