32.8 MPDDRC Memory Device Register
This register can only be written if the WPEN bit is cleared in the MPDDRC Write Protection Mode Register.
| Name: | MPDDRC_MD |
| Offset: | 0x20 |
| Reset: | 0x00000013 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DBW | MD[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 1 | 0 | 1 | 1 | |||||
Bit 4 – DBW Data Bus Width
| Value | Name | Description |
|---|---|---|
| 0 | – |
Reserved |
| 1 | DBW_16_BITS | Data bus width is 16 bits. |
Bits 2:0 – MD[2:0] Memory Device
| Value | Name | Description |
|---|---|---|
| 3 | LPDDR_SDRAM | Low-power DDR1-SDRAM |
| 6 | DDR2_SDRAM | DDR2-SDRAM |