32.9 MPDDRC I/O Calibration Register
| Name: | MPDDRC_IO_CALIBR |
| Offset: | 0x34 |
| Reset: | 0x00870000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CALCODEN[3:0] | CALCODEP[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TZQIO[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CK_F_RANGE[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bits 23:20 – CALCODEN[3:0] Number of N-type Transistors
Gives the number of N-type transistors to perform the calibration.
Bits 19:16 – CALCODEP[3:0] Number of P-type Transistors
Gives the number of P-type transistors to perform the calibration.
Bits 14:8 – TZQIO[6:0] IO Calibration
Defines the delay between the start up of the amplifier and the beginning of the calibration, in number of DDRCK clock cycles. The value of this field must be set to 600 ns. The number of cycles is between 0 and 127.
The TZQIO configuration code must be set correctly depending on the clock
frequency using the following formula:
- TZQIO = (DDRCK × (600 × 10-9)) + 1
where the DDRCK frequency is in Hz.
For example, for a frequency of 176 MHz, the value of the TZQIO field is configured (176 × 106) × (600 × 10-9) + 1.
Bits 2:0 – CK_F_RANGE[2:0] DDRCK Maximum Clock Frequency Range
This field is written only once at the initialization sequence and is always written to 7 whatever the frequency configured on DDRCK.