32.10 MPDDRC OCMS Register
This register can only be written if the WPEN bit is cleared in the MPDDRC Write Protection Mode Register.
Name: | MPDDRC_OCMS |
Offset: | 0x38 |
Reset: | 0x00000000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
TAMPCLR | SCR_EN | ||||||||
Access | R/W | R/W | |||||||
Reset | 0 | 0 |
Bit 4 – TAMPCLR Tamper Clear Enable
Value | Description |
---|---|
0 | A tamper detection event has no effect on MPDDRC scrambling keys. |
1 | A tamper detection event immediately clears MPDDRC scrambling keys. |
Bit 0 – SCR_EN Scrambling Enable
Value | Description |
---|---|
0 | Disables “Off-chip” scrambling for SDRAM access. |
1 | Enables “Off-chip” scrambling for SDRAM access. |