48.10.11 SDMMC Host Control 1 Register (e.MMC)
| Name: | SDMMC_HC1R (e.MMC) |
| Offset: | 0x28 |
| Reset: | 0x00 |
| Property: | Read/Write |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EXTDW | DMASEL[1:0] | HSEN | DW | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 5 – EXTDW Extended Data Width
This bit controls the 8-bit Bus Width mode for embedded devices. Support of this function is indicated in 8-bit Support for Embedded Device in SDMMC_CA0R. If a device supports the 8-bit mode, this may be set to 1. If this bit is 0, the bus width is controlled by Data Width (DW).
Bits 4:3 – DMASEL[1:0] DMA Select
One of the supported DAM modes can be selected. The DMA modes supported are given in SDMMC_CA0R. Use of selected DMA is determined by DMA Enable (DMAEN) in SDMMC_TMR.
| Value | Name | Description |
|---|---|---|
| 0 | SDMA | SDMA is selected |
| 1 | – | Reserved |
| 2 | ADMA32 | 32-bit Address ADMA2 is selected |
| 3 | – |
Reserved |
Bit 2 – HSEN High Speed Enable
Before setting this bit, the user must check High Speed Support (HSSUP) in SDMMC_CA0R.
If this bit is set to 0 (default), the SDMMC outputs CMD line and DAT lines at the falling edge of the SD clock (up to 25 MHz). If this bit is set to 1, the SDMMC outputs the CMD line and the DAT lines at the rising edge of the SD clock (up to 50 MHz).
If Preset Value Enable (PVALEN) in SDMMC_HC2R is set to 1, the user needs to reset the SD Clock Enable (SDCLKEN) before changing this bit to avoid generating clock glitches. After setting this bit to 1, the user sets SDCLEN to 1 again.
| Value | Description |
|---|---|
| 0 | Normal Speed mode. |
| 1 | High Speed mode. |
Bit 1 – DW Data Width
This bit selects the data width of the SDMMC. It must be set to match the data width of the card.
0 (1_BIT): 1-bit mode.
1 (4_BIT): 4-bit mode.