48.10.45 SDMMC e.MMC Control 1 Register
| Name: | SDMMC_MC1R |
| Offset: | 0x204 |
| Reset: | 0x00 |
| Property: | Read/Write |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BOOTA | OPD | DDR | CMDTYP[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 5 – BOOTA e.MMC Boot Acknowledge Enable
This bit must be set according to the value of BOOT_ACK in the Extended CSD Register (see “Embedded MultiMedia Card (e.MMC) Electrical Standard 4.51” ).
When this bit is set to 1, the SDMMC waits for boot acknowledge pattern from the e.MMC before receiving boot data.
If the boot acknowledge pattern is wrong, the BOOTAE status flag rises in SDMMC_EISTR if BOOTAE is set in SDMMC_EISTER. An interrupt is generated if BOOTAE is set in SDMMC_EISIER.
If the no boot acknowledge pattern is received, the DATTEO status flag rises in SDMMC_EISTR if DATTEO is set in SDMMC_EISTER. An interrupt is generated if DATTEO is set in SDMMC_EISIER.
Bit 4 – OPD e.MMC Open Drain Mode
This bit sets the command line in open drain.
| Value | Description |
|---|---|
| 0 | The command line is in push-pull. |
| 1 | The command line is in open drain. |
Bit 3 – DDR e.MMC HSDDR Mode
This bit selects the High Speed DDR mode.
The clock divider (DIV) in SDMMC_CCR must be set to a value different from 0 when DDR is 1.
| Value | Description |
|---|---|
| 0 | High Speed DDR is not selected. |
| 1 | High Speed DDR is selected. |
Bits 1:0 – CMDTYP[1:0] e.MMC Command Type
| Value | Name | Description |
|---|---|---|
| 0 | NORMAL | The command is not an e.MMC specific command. |
| 1 | WAITIRQ | This bit must be set to 1 when the e.MMC is in Interrupt mode (CMD40). See “Interrupt Mode” in the “Embedded MultiMedia Card (e.MMC) Electrical Standard 4.51” . |
| 2 | STREAM | This bit must be set to 1 in the case of Stream Read(CMD11) or Stream Write (CMD20). Only effective for e.MMC up to revision 4.41. |
| 3 | BOOT | Starts a Boot Operation mode at the next write to SDMMC_CR. Boot data are read directly from e.MMC device. |