48.10.6 SDMMC Command Register
| Name: | SDMMC_CR |
| Offset: | 0x0E |
| Reset: | 0x0000 |
| Property: | Read/Write |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CMDIDX[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CMDTYP[1:0] | DPSEL | CMDICEN | CMDCCEN | RESPTYP[1:0] | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 13:8 – CMDIDX[5:0] Command Index
This bit shall be set to the command number (CMD0–63, ACMD0–63) that is specified in bits 45–40 of the Command-Format in the “Physical Layer Simplified Specification V3.01” , “SDIO Simplified Specification V3.00” , and “Embedded MultiMedia Card (e.MMC) Electrical Standard 4.51” .
Bits 7:6 – CMDTYP[1:0] Command Type
| Value | Name | Description |
|---|---|---|
| 0 | NORMAL | Other commands |
| 1 | SUSPEND | CMD52 to write “Bus Suspend” in the Card Common Control registers (CCCR) (for SDIO only) |
| 2 | RESUME | CMD52 to write “Function Select” in the Card Common Control registers (CCCR) (for SDIO only) |
| 3 | ABORT | CMD12, CMD52 to write “I/O Abort” in the Card Common Control registers (CCCR) (for SDIO only) |
Bit 5 – DPSEL Data Present Select
This bit is set to 1 to indicate that data is present and shall be transferred using the DAT lines. It is set to 0 for the following:
- Commands using only CMD line (Ex. CMD52)
- Commands with no data transfer but using Busy signal on DAT[0] line (Ex. CMD38)
- Resume command
| Value | Description |
|---|---|
| 0 | No data present |
| 1 | Data present |
Bit 4 – CMDICEN Command Index Check Enable
If this bit is set to 1, the SDMMC checks the Index field in the response to see if it has the same value as the command index. If it has not, it is reported as a Command Index Error (CMDIDX) in SDMMC_EISTR. If this bit is set to 0, the Index field of the response is not checked.
0 (DISABLED): The Command Index Check is disabled.
1 (ENABLED): The Command Index Check is enabled.
Bit 3 – CMDCCEN Command CRC Check Enable
If this bit is set to 1, the SDMMC checks the CRC field in the response. If an error is detected, it is reported as a Command CRC Error (CMDCRC) in SDMMC_EISTR. If this bit is set to 0, the CRC field is not checked. The position of the CRC field is determined according to the length of the response.
0 (DISABLED): The Command CRC Check is disabled.
1 (ENABLED): The Command CRC Check is enabled.
Bits 1:0 – RESPTYP[1:0] Response Type
This field is set according to the response type expected for the command index (CMDIDX).
| Value | Name | Description |
|---|---|---|
| 0 | NORESP | No Response |
| 1 | RL136 | Response Length 136 |
| 2 | RL48 | Response Length 48 |
| 3 | RL48BUSY | Response Length 48 with Busy |