48.10 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	SDMMC_SSAR	31:24	ADDR/ARG2[31:24]
		23:16	ADDR/ARG2[23:16]
		15:8	ADDR/ARG2[15:8]
		7:0	ADDR/ARG2[7:0]
0x04	SDMMC_BSR	15:8		BOUNDARY[2:0]					BLKSIZE[9:8]
0x04	SDMMC_BSR	7:0	BLKSIZE[7:0]
0x06	SDMMC_BCR	15:8	BLKCNT[15:8]
0x06	SDMMC_BCR	7:0	BLKCNT[7:0]
0x08	SDMMC_ARG1R	31:24	ARG1[31:24]
		23:16	ARG1[23:16]
		15:8	ARG1[15:8]
		7:0	ARG1[7:0]
0x0C	SDMMC_TMR	15:8
0x0C	SDMMC_TMR	7:0			MSBSEL	DTDSEL	ACMDEN[1:0]		BCEN	DMAEN
0x0E	SDMMC_CR	15:8			CMDIDX[5:0]
0x0E	SDMMC_CR	7:0	CMDTYP[1:0]		DPSEL	CMDICEN	CMDCCEN		RESPTYP[1:0]
0x10	SDMMC_RR0	31:24	CMDRESP[31:24]
		23:16	CMDRESP[23:16]
		15:8	CMDRESP[15:8]
		7:0	CMDRESP[7:0]
0x14	SDMMC_RR1	31:24	CMDRESP[31:24]
		23:16	CMDRESP[23:16]
		15:8	CMDRESP[15:8]
		7:0	CMDRESP[7:0]
0x18	SDMMC_RR2	31:24	CMDRESP[31:24]
		23:16	CMDRESP[23:16]
		15:8	CMDRESP[15:8]
		7:0	CMDRESP[7:0]
0x1C	SDMMC_RR3	31:24	CMDRESP[31:24]
		23:16	CMDRESP[23:16]
		15:8	CMDRESP[15:8]
		7:0	CMDRESP[7:0]
0x20	SDMMC_BDPR	31:24	BUFDATA[31:24]
		23:16	BUFDATA[23:16]
		15:8	BUFDATA[15:8]
		7:0	BUFDATA[7:0]
0x24	SDMMC_PSR	31:24								CMDLL
		23:16	DATLL[3:0]
		15:8					BUFRDEN	BUFWREN	RTACT	WTACT
		7:0						DLACT	CMDINHD	CMDINHC
0x28	SDMMC_HC1R (SD_SDIO)	7:0		CARDDTL		DMASEL[1:0]		HSEN	DW	LEDCTRL
0x28	SDMMC_HC1R (e.MMC)	7:0			EXTDW	DMASEL[1:0]		HSEN	DW
0x29	SDMMC_PCR	7:0								SDBPWR
0x2A	SDMMC_BGCR (SD_SDIO)	7:0					INTBG	RWCTRL	CONTR	STPBGR
0x2A	SDMMC_BGCR (e.MMC)	7:0							CONTR	STPBGR
0x2B	SDMMC_WCR (SD_SDIO)	7:0								WKENCINT
0x2C	SDMMC_CCR	15:8	SDCLKFSEL[7:0]
0x2C	SDMMC_CCR	7:0	USDCLKFSEL[1:0]		CLKGSEL			SDCLKEN	INTCLKS	INTCLKEN
0x2E	SDMMC_TCR	7:0					DTCVAL[3:0]
0x2F	SDMMC_SRR	7:0						SWRSTDAT	SWRSTCMD	SWRSTALL
0x30	SDMMC_NISTR (SD_SDIO)	15:8	ERRINT							CINT
0x30	SDMMC_NISTR (SD_SDIO)	7:0			BRDRDY	BWRRDY	DMAINT	BLKGE	TRFC	CMDC
0x30	SDMMC_NISTR (e.MMC)	15:8	ERRINT	BOOTAR
0x30	SDMMC_NISTR (e.MMC)	7:0			BRDRDY	BWRRDY	DMAINT	BLKGE	TRFC	CMDC
0x32	SDMMC_EISTR (SD_SDIO)	15:8							ADMA	ACMD
0x32	SDMMC_EISTR (SD_SDIO)	7:0	CURLIM	DATEND	DATCRC	DATTEO	CMDIDX	CMDEND	CMDCRC	CMDTEO
0x32	SDMMC_EISTR (e.MMC)	15:8				BOOTAE			ADMA	ACMD
0x32	SDMMC_EISTR (e.MMC)	7:0	CURLIM	DATEND	DATCRC	DATTEO	CMDIDX	CMDEND	CMDCRC	CMDTEO
0x34	SDMMC_NISTER (SD_SDIO)	15:8								CINT
0x34	SDMMC_NISTER (SD_SDIO)	7:0			BRDRDY	BWRRDY	DMAINT	BLKGE	TRFC	CMDC
0x34	SDMMC_NISTER (e.MMC)	15:8		BOOTAR
0x34	SDMMC_NISTER (e.MMC)	7:0			BRDRDY	BWRRDY	DMAINT	BLKGE	TRFC	CMDC
0x36	SDMMC_EISTER (SD_SDIO)	15:8							ADMA	ACMD
0x36	SDMMC_EISTER (SD_SDIO)	7:0	CURLIM	DATEND	DATCRC	DATTEO	CMDIDX	CMDEND	CMDCRC	CMDTEO
0x36	SDMMC_EISTER (e.MMC)	15:8				BOOTAE			ADMA	ACMD
0x36	SDMMC_EISTER (e.MMC)	7:0	CURLIM	DATEND	DATCRC	DATTEO	CMDIDX	CMDEND	CMDCRC	CMDTEO
0x38	SDMMC_NISIER (SD_SDIO)	15:8								CINT
0x38	SDMMC_NISIER (SD_SDIO)	7:0			BRDRDY	BWRRDY	DMAINT	BLKGE	TRFC	CMDC
0x38	SDMMC_NISIER (e.MMC)	15:8		BOOTAR
0x38	SDMMC_NISIER (e.MMC)	7:0			BRDRDY	BWRRDY	DMAINT	BLKGE	TRFC	CMDC
0x3A	SDMMC_EISIER (SD_SDIO)	15:8							ADMA	ACMD
0x3A	SDMMC_EISIER (SD_SDIO)	7:0	CURLIM	DATEND	DATCRC	DATTEO	CMDIDX	CMDEND	CMDCRC	CMDTEO
0x3A	SDMMC_EISIER (e.MMC)	15:8				BOOTAE			ADMA	ACMD
0x3A	SDMMC_EISIER (e.MMC)	7:0	CURLIM	DATEND	DATCRC	DATTEO	CMDIDX	CMDEND	CMDCRC	CMDTEO
0x3C	SDMMC_ACESR	15:8
0x3C	SDMMC_ACESR	7:0	CMDNI			ACMDIDX	ACMDEND	ACMDCRC	ACMDTEO	ACMD12NE
0x3E	SDMMC_HC2R (SD_SDIO)	15:8	PVALEN	ASINTEN
0x3E	SDMMC_HC2R (SD_SDIO)	7:0
0x3E	SDMMC_HC2R (e.MMC)	15:8	PVALEN
0x3E	SDMMC_HC2R (e.MMC)	7:0
0x40	SDMMC_CA0R	31:24	SLTYPE[1:0]		ASINTSUP	SB64SUP		V18VSUP	V30VSUP	V33VSUP
		23:16	SRSUP	SDMASUP	HSSUP		ADMA2SUP	ED8SUP	MAXBLKL[1:0]
		15:8	BASECLKF[7:0]
		7:0	TEOCLKU		TEOCLKF[5:0]
0x44	SDMMC_CA1R	31:24
		23:16	CLKMULT[7:0]
		15:8
		7:0		DRVDSUP	DRVCSUP	DRVASUP		DDR50SUP	SDR104SUP	SDR50SUP
0x48	SDMMC_MCCAR	31:24
		23:16	MAXCUR18V[7:0]
		15:8	MAXCUR30V[7:0]
		7:0	MAXCUR33V[7:0]
0x4C ... 0x4F	Reserved
0x50	SDMMC_FERACES	15:8
0x50	SDMMC_FERACES	7:0	CMDNI			ACMDIDX	ACMDEND	ACMDCRC	ACMDTEO	ACMD12NE
0x52	SDMMC_FEREIS	15:8				BOOTAE			ADMA	ACMD
0x52	SDMMC_FEREIS	7:0	CURLIM	DATEND	DATCRC	DATTEO	CMDIDX	CMDEND	CMDCRC	CMDTEO
0x54	SDMMC_AESR	7:0						LMIS	ERRST[1:0]
0x55 ... 0x57	Reserved
0x58	SDMMC_ASAR0	31:24	ADMASA[31:24]
		23:16	ADMASA[23:16]
		15:8	ADMASA[15:8]
		7:0	ADMASA[7:0]
0x5C ... 0x5F	Reserved
0x60	SDMMC_PVR0	15:8						CLKGSEL	SDCLKFSEL[9:8]
0x60	SDMMC_PVR0	7:0	SDCLKFSEL[7:0]
0x62	SDMMC_PVR1	15:8						CLKGSEL	SDCLKFSEL[9:8]
0x62	SDMMC_PVR1	7:0	SDCLKFSEL[7:0]
0x64	SDMMC_PVR2	15:8						CLKGSEL	SDCLKFSEL[9:8]
0x64	SDMMC_PVR2	7:0	SDCLKFSEL[7:0]
0x66	SDMMC_PVR3	15:8						CLKGSEL	SDCLKFSEL[9:8]
0x66	SDMMC_PVR3	7:0	SDCLKFSEL[7:0]
0x68 ... 0xFB	Reserved
0xFC	SDMMC_SISR	15:8
0xFC	SDMMC_SISR	7:0							INTSSL[1:0]
0xFE	SDMMC_HCVR	15:8	VVER[7:0]
0xFE	SDMMC_HCVR	7:0	SVER[7:0]
0x0100 ... 0x01FF	Reserved
0x0200	SDMMC_APSR	31:24
		23:16
		15:8
		7:0					HDATLL[3:0]
0x0204	SDMMC_MC1R	7:0			BOOTA	OPD	DDR		CMDTYP[1:0]
0x0205	SDMMC_MC2R	7:0							ABOOT	SRESP
0x0206 ... 0x0207	Reserved
0x0208	SDMMC_ACR	31:24
		23:16
		15:8
		7:0							BMAX[1:0]
0x020C	SDMMC_CC2R	31:24
		23:16
		15:8
		7:0								FSDCLKD
0x0210 ... 0x022F	Reserved
0x0230	SDMMC_CACR	31:24
		23:16
		15:8	KEY[7:0]
		7:0								CAPWREN
0x0234	SDMMC_DBGR	31:24
		23:16
		15:8
		7:0								NIDBG