48.10.18 SDMMC Software Reset Register
| Name: | SDMMC_SRR |
| Offset: | 0x2F |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SWRSTDAT | SWRSTCMD | SWRSTALL | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 2 – SWRSTDAT Software Reset for DAT Line
Only part of a data circuit is reset. The DMA circuit is also reset.
The following registers and bits are cleared by this bit:
- SDMMC Buffer Data Port Register
- Buffer is cleared and initialized.
- SDMMC Present State Register
- Buffer Read Enable (BUFRDEN)
- Buffer Write Enable (BUFWREN)
- Read Transfer Active (RTACT)
- Write Transfer Active (WTACT)
- DAT Line Active (DATLL)
- Command Inhibit (DAT) (CMDINHD)
- SDMMC Block Gap Control Register
(SD_SDIO)
- Continue Request (CONTR)
- Stop At Block Gap Request (STPBGR)
- SDMMC Normal Interrupt Status Register
(SD_SDIO)
- Buffer Read Ready (BRDRDY)
- Buffer Write Ready (BWRRDY)
- DMA Interrupt (DMAINT)
- Block Gap Event (BLKGE)
- Transfer Complete (TRFC)
| Value | Description |
|---|---|
| 0 | Work |
| 1 | Reset |
Bit 1 – SWRSTCMD Software Reset for CMD Line
Only part of a command circuit is reset.
The following registers and bits are cleared by this bit:
- SDMMC Present State Register
- Command Inhibit (CMD) (CMDINHC)
- SDMMC Normal Interrupt Status Register
(SD_SDIO) and SDMMC Normal Interrupt Status Register
(e.MMC)
- Command Complete (CMDC)
| Value | Description |
|---|---|
| 0 | Work |
| 1 | Reset |
Bit 0 – SWRSTALL Software Reset for All
This reset affects the entire SDMMC. During initialization, the SDMMC must be reset by setting this bit to '1'. This bit is automatically cleared to '0' when SDMMC_CA0R and SDMMC_CA1R are valid and the user can read them. If this bit is set to '1', the user should issue a reset command and reinitialize the card.
List of registers cleared to '0':
- SDMMC SDMA System Address / Argument 2 Register
- SDMMC Block Size Register
- SDMMC Block Count Register
- SDMMC Argument 1 Register
- SDMMC Command Register
- SDMMC Transfer Mode Register
- SDMMC Response Register
- SDMMC Buffer Data Port Register
- SDMMC Present State Register (except CMDLL, DATLL, WRPPL, CARDDDPL, CARDSS, CARDINS)
- SDMMC Host Control 1 Register (SD_SDIO)
- SDMMC Host Control 1 Register (e.MMC)
- SDMMC Power Control Register
- SDMMC Block Gap Control Register (SD_SDIO)
- SDMMC Block Gap Control Register (e.MMC)
- SDMMC Wakeup Control Register (SD_SDIO)
- SDMMC Clock Control Register
- SDMMC Timeout Control Register
- SDMMC Normal Interrupt Status Register (SD_SDIO)
- SDMMC Error Interrupt Status Register (SD_SDIO)
- SDMMC Normal Interrupt Status Enable Register (SD_SDIO)
- SDMMC Error Interrupt Status Enable Register (SD_SDIO)
- SDMMC Normal Interrupt Signal Enable Register (SD_SDIO)
- SDMMC Error Interrupt Signal Enable Register (SD_SDIO)
- SDMMC Auto CMD Error Status Register
- SDMMC Host Control 2 Register (SD_SDIO)
- SDMMC ADMA Error Status Register
- SDMMC ADMA System Address Register
- SDMMC Slot Interrupt Status Register
- SDMMC e.MMC Control 1 Register
- SDMMC e.MMC Control 2 Register
- SDMMC AHB Control Register
- SDMMC Clock Control 2 Register
- SDMMC Capabilities Control Register (except KEY)
| Value | Description |
|---|---|
| 0 | Work |
| 1 | Reset |