48.10.32 SDMMC Host Control 2 Register (SD_SDIO)
| Name: | SDMMC_HC2R (SD_SDIO) |
| Offset: | 0x3E |
| Reset: | 0x0000 |
| Property: | Read/Write |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PVALEN | ASINTEN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bit 15 – PVALEN Preset Value Enable
As the operating SDCLK frequency and I/O driver strength depend on the system implementation, it is difficult to determine these parameters in the standard host driver. When PVALEN is set to 1, automatic SDCLK frequency generation and driver strength selection are performed without considering system-specific conditions. This bit enables the functions defined in SDMMC_PVR.
If this bit is set to 0, SDMMC_CCR.SDCLKFSEL and SDMMC_CCR.CLKGSEL are set by the user.
If this bit is set to 1, SDMMC_CCR.SDCLKFSEL and SDMMC_CCR.CLKGSEL are set by the SDMMC as specified in SDMMC_PVR.
| Value | Description |
|---|---|
| 0 | SDCLK and Driver strength are controlled by the user. |
| 1 | Automatic selection by Preset Value is enabled. |
Bit 14 – ASINTEN Asynchronous Interrupt Enable
This bit can be set to 1 if a card supports asynchronous interrupts and Asynchronous Interrupt Support (ASINTSUP) is set to 1 in SDMMC_CA0R. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode. If this bit is set to 1, the user can stop the SDCLK during the asynchronous interrupt period to save power. During this period, the SDMMC continues to deliver the Card Interrupt to the host when it is asserted by the card.
| Value | Description |
|---|---|
| 0 | Disabled |
| 1 | Enabled |