48.10.48 SDMMC Clock Control 2 Register
| Name: | SDMMC_CC2R |
| Offset: | 0x20C |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FSDCLKD | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – FSDCLKD Force SDCLK Disabled
The user can choose to maintain the SDCLK during 8 SDCLK cycles after the end bit of the last data block in case of a read transaction, or after the end bit of the CRC status in case of a write transaction.
| Value | Description |
|---|---|
| 0 | The SDCLK is forced and it cannot be stopped immediately after the transaction. |
| 1 | The SDCLK is not forced and it can be stopped immediately after the transaction. |