48.10.33 SDMMC Host Control 2 Register (e.MMC)
Note: This register configuration is specific to the e.MMC operation mode.
| Name: | SDMMC_HC2R (e.MMC) |
| Offset: | 0x3E |
| Reset: | 0x0000 |
| Property: | Read/Write |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PVALEN | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bit 15 – PVALEN Preset Value Enable
As the operating SDCLK frequency and I/O driver strength depend on the system implementation, it is difficult to determine these parameters in the standard host driver. When Preset Value Enable (PVALEN) is set to 1, automatic SDCLK frequency generation and driver strength selection are performed without considering system-specific conditions. This bit enables the functions defined in SDMMC_PVR.
If this bit is set to 0, SDMMC_CCR.SDCLKFSEL and SDMMC_CCR.CLKGSEL are set by the user.
If this bit is set to 1, SDMMC_CCR.SDCLKFSEL and SDMMC_CCR.CLKGSEL are set by the SDMMC as specified in SDMMC_PVR.
| Value | Description |
|---|---|
| 0 | SDCLK and Driver strength are controlled by the user. |
| 1 | Automatic selection by Preset Value is enabled. |