48.10.42 SDMMC Slot Interrupt Status Register
| Name: | SDMMC_SISR |
| Offset: | 0xFC |
| Reset: | 0x0000 |
| Property: | Read-only |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| INTSSL[1:0] | |||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 | |||||||
Bits 1:0 – INTSSL[1:0] Interrupt Signal for Each Slot
These status bits indicate the logical OR of Interrupt Signals and Wakeup Signal for each SDMMC instance in the product (INTSSL[x] corresponds to SDMMCx instance in the product).