48.10.31 SDMMC Auto CMD Error Status Register

Name: SDMMC_ACESR
Offset: 0x3C
Reset: 0x0000
Property: Read-only

Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
 CMDNI  ACMDIDXACMDENDACMDCRCACMDTEOACMD12NE 
Access RRRRRR 
Reset 000000 

Bit 7 – CMDNI Command Not Issued by Auto CMD12 Error

This bit is set to 1 when CMD_wo_DAT is not executed due to an Auto CMD12 error (SDMMC_ACESR[4:1]). This bit is set to 0 when Auto CMD Error is generated by Auto CMD23.

ValueDescription
0

No error.

1

Error.

Bit 4 – ACMDIDX Auto CMD Index Error

This bit is set to 1 when the Command Index error occurs in response to a command.

ValueDescription
0

No error.

1

Error.

Bit 3 – ACMDEND Auto CMD End Bit Error

This bit is set to 1 when detecting that the end bit of the command response is 0.

ValueDescription
0

No error.

1

Error.

Bit 1 – ACMDTEO Auto CMD Timeout Error

This bit is set to 1 if no response is returned within 64 SDCLK cycles from the end bit of the command. If this bit is set to 1, the other error status bits (SDMMC_ACESR[4:2]) are meaningless.

Table 48-4. Relation between ACMDCRC and ACMDTEO
ACMDCRC ACMDTEO Error Types
0 0 No error
0 1 Response Timeout error
1 0 Response CRC error
1 1 CMD line conflict

Bit 0 – ACMD12NE Auto CMD12 Not Executed

If a memory multiple block data transfer is not started due to a command error, this bit is not set to 1 because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the SDMMC cannot issue Auto CMD12 to stop a memory multiple block data transfer due to some error. If this bit is set to 1, other error status bits (SDMMC_ACESR[4:1]) are meaningless.

This bit is set to 0 when an Auto CMD error is generated by Auto CMD23.

ValueDescription
0 No error.
1 Error.