5.6.6 CSI D-PHY Receive Status Register
| Name: | CSI_PHY_RX |
| Offset: | 0x48 |
| Reset: | 0x00010000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PHY_RXCLKACTIVEHS | PHY_RXULPSSCLKNOT | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 1 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PHY_RXULPSESC_3 | PHY_RXULPSESC_2 | PHY_RXULPSESC_1 | PHY_RXULPSESC_0 | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 17 – PHY_RXCLKACTIVEHS D-PHY Receives a DDR Clock
| Value | Description |
|---|---|
| 0 | No DDR clock received. |
| 1 | Indicates that D-PHY clock lane is actively receiving a DDR clock. |
Bit 16 – PHY_RXULPSSCLKNOT Clock Lane Power Status
| Value | Description |
|---|---|
| 0 | Indicates that D-PHY Clock Lane module has entered Ultra-Low-Power (ULP) mode. |
| 1 | Clock Lane is not in ULP mode. |
Bit 3 – PHY_RXULPSESC_3 Lane 3 Ultra-Low-Power Status
| Value | Description |
|---|---|
| 0 | Indicates that D-PHY Clock Lane module has entered ULP mode. |
| 1 | Clock Lane is not in ULP mode. |
Bit 2 – PHY_RXULPSESC_2 Data Lane 2 Ultra-Low-Power Status
| Value | Description |
|---|---|
| 0 | Data lane 2 module is not in ULP mode. |
| 1 | Data lane 2 module has entered ULP mode. |
Bit 1 – PHY_RXULPSESC_1 Data Lane 1 Ultra-Low-Power Status
| Value | Description |
|---|---|
| 0 | Data lane 1 module is not in ULP mode. |
| 1 | Data lane 1 module has entered ULP mode. |
Bit 0 – PHY_RXULPSESC_0 Data Lane 0 Ultra-Low-Power Status
| Value | Description |
|---|---|
| 0 | Data lane 0 module is not in ULP mode. |
| 1 | Data lane 0 module has entered ULP mode. |