Interrupt mask for CSI_INT_MSK_PHY controls which interrupt status bits trigger the
interrupt pin.
The following configuration values are valid for all listed bit names of this
register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
Name:
CSI_INT_MSK_PHY
Offset:
0x114
Reset:
0x00000000
Property:
Read/Write
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
MASK_PHY_ERRESC_3
MASK_PHY_ERRESC_2
MASK_PHY_ERRESC_1
MASK_PHY_ERRESC_0
Access
R/W
R/W
R/W
R/W
Reset
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
MASK_PHY_ERRSOTHS_3
MASK_PHY_ERRSOTHS_2
MASK_PHY_ERRSOTHS_1
MASK_PHY_ERRSOTHS_0
Access
R/W
R/W
R/W
R/W
Reset
0
0
0
0
Bit 19 – MASK_PHY_ERRESC_3 Start of Transmission Error on Data Lane 3 (synchronization can
still be achieved) Interrupt Mask
Bit 18 – MASK_PHY_ERRESC_2 Start of Transmission Error on Data Lane 2 (synchronization can
still be achieved) Interrupt Mask
Bit 17 – MASK_PHY_ERRESC_1 Start of Transmission Error on Data Lane 1 (synchronization can
still be achieved) Interrupt Mask
Bit 16 – MASK_PHY_ERRESC_0 Start of Transmission Error
on Data Lane 0 (synchronization can still be achieved) Interrupt
Mask
Bit 3 – MASK_PHY_ERRSOTHS_3 Start of Transmission Error on Data Lane 3 (no synchronization
achieved) Interrupt Mask
Bit 2 – MASK_PHY_ERRSOTHS_2 Start of Transmission Error on Data Lane 2 (no synchronization
achieved) Interrupt Mask
Bit 1 – MASK_PHY_ERRSOTHS_1 Start of Transmission Error on Data Lane 1 (no synchronization
achieved) Interrupt Mask
Bit 0 – MASK_PHY_ERRSOTHS_0 Start of Transmission Error
on Data Lane 0 (no synchronization achieved) Interrupt Mask
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
