5.6.1 CSI Lane Configuration Register
| Name: | CSI_N_LANES |
| Offset: | 0x4 |
| Reset: | 0x00000001 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| N_LANES[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 1 | |||||||
Bits 1:0 – N_LANES[1:0] Number of active data lanes
The update can be performed only when the D-PHY is in Stop state.
| Value | Name | Description |
|---|---|---|
| 0 | 1_LANE | One data lane |
| 1 | 2_LANES | Two data lanes |
| 2 | 3_LANES | Three data lanes |
| 3 | 4_LANES | Four data lanes |