The following configuration values are valid for all listed bit names of this
register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
Name:
CSI_INT_MSK_PHY_FATAL
Offset:
0xE4
Reset:
0x00000000
Property:
Read/Write
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
MASK_ERRSOTSYNCHS_3
MASK_ERRSOTSYNCHS_2
MASK_ERRSOTSYNCHS_1
MASK_ERRSOTSYNCHS_0
Access
R/W
R/W
R/W
R/W
Reset
0
0
0
0
Bit 3 – MASK_ERRSOTSYNCHS_3 Data Lane 3 Start
Of Transmission Error Interrupt Mask
Bit 2 – MASK_ERRSOTSYNCHS_2 Data Lane 2 Start
Of Transmission Error Interrupt Mask
Bit 1 – MASK_ERRSOTSYNCHS_1 Data Lane 1 Start Of
Transmission Error Interrupt Mask
Bit 0 – MASK_ERRSOTSYNCHS_0 Data Lane 0 Start Of
Transmission Error Interrupt Mask
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
