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5.6.15 CSI Packet Fatal Error Interrupt
Mask Register Interrupt mask for CSI_INT_ST_PKT_FATAL controls which interrupt status bits trigger
the interrupt pin.
The following configuration values are valid for all listed bit names of
this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
Name: CSI_INT_MSK_PKT_FATAL Offset: 0xF4 Reset: 0x00000000 Property: Read/Write
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 MASK_ERR_ECC_DOUBLE Access R/W Reset 0
Bit 15 14 13 12 11 10 9 8 Access Reset
Bit 7 6 5 4 3 2 1 0 MASK_VC3_ERR_CRC MASK_VC2_ERR_CRC MASK_VC1_ERR_CRC MASK_VC0_ERR_CRC Access R/W R/W R/W R/W Reset 0 0 0 0
Bit 16 – MASK_ERR_ECC_DOUBLE Unrecoverable Header Error
(ECC Two Errors) Interrupt Mask
Bit 3 – MASK_VC3_ERR_CRC Virtual Channel 3 Payload Checksum Error Interrupt
Mask
Bit 2 – MASK_VC2_ERR_CRC Virtual Channel 2 Payload Checksum Error Interrupt
Mask
Bit 1 – MASK_VC1_ERR_CRC Virtual Channel 1 Payload Checksum Error Interrupt
Mask
Bit 0 – MASK_VC0_ERR_CRC Virtual Channel 0 Payload
Checksum Error Interrupt Mask
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