Reading CSI_INT_ST_PHY does not clear the interrupt pin.
The following configuration values are valid for all listed bit names of this
register:
0: No event occurred since the last read of the register.
1: An event occurred since the last read of the register.
Name:
CSI_INT_ST_PHY
Offset:
0x110
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
PHY_ERRESC_3
PHY_ERRESC_2
PHY_ERRESC_1
PHY_ERRESC_0
Access
R
R
R
R
Reset
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
PHY_ERRSOTHS_3
PHY_ERRSOTHS_2
PHY_ERRSOTHS_1
PHY_ERRSOTHS_0
Access
R
R
R
R
Reset
0
0
0
0
Bit 19 – PHY_ERRESC_3 Start of Transmission Error on Data Lane 3 (synchronization can
still be achieved) (cleared on read)
Bit 18 – PHY_ERRESC_2 Start of Transmission Error on Data Lane 2 (synchronization can
still be achieved) (cleared on read)
Bit 17 – PHY_ERRESC_1 Start of Transmission Error on Data Lane 1 (synchronization can
still be achieved) (cleared on read)
Bit 16 – PHY_ERRESC_0 Start of Transmission Error
on Data Lane 0 (synchronization can still be achieved) (cleared on
read)
Bit 3 – PHY_ERRSOTHS_3 Start of Transmission Error on Data Lane 3 (no synchronization
achieved) (cleared on read)
Bit 2 – PHY_ERRSOTHS_2 Start of Transmission Error on Data Lane 2 (no synchronization
achieved) (cleared on read)
Bit 1 – PHY_ERRSOTHS_1 Start of Transmission Error on Data Lane 1 (no synchronization
achieved) (cleared on read)
Bit 0 – PHY_ERRSOTHS_0 Start of Transmission Error
on Data Lane 0 (no synchronization achieved) (cleared on
read)
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
