5.6.22 CSI D-PHY Interrupt Force Register

Used for test purposes. Triggers INT_ST_PHY interrupt events individually without the need to activate the conditions that trigger the interrupt sources.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: The corresponding interrupt source is forced.

Name: CSI_INT_FORCE_PHY
Offset: 0x118
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     FORCE_PHY_ERRESC_3FORCE_PHY_ERRESC_2FORCE_PHY_ERRESC_1FORCE_PHY_ERRESC_0 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
     FORCE_PHY_ERRSOTHS_3FORCE_PHY_ERRSOTHS_2FORCE_PHY_ERRSOTHS_1FORCE_PHY_ERRSOTHS_0 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 19 – FORCE_PHY_ERRESC_3 Force Start of Transmission Error on Data Lane 3 (synchronization can still be achieved) Interrupt

Bit 18 – FORCE_PHY_ERRESC_2 Force Start of Transmission Error on Data Lane 2 (synchronization can still be achieved) Interrupt

Bit 17 – FORCE_PHY_ERRESC_1 Force Start of Transmission Error on Data Lane 1 (synchronization can still be achieved) Interrupt

Bit 16 – FORCE_PHY_ERRESC_0 Force Start of Transmission Error on Data Lane 0 (synchronization can still be achieved) Interrupt

Bit 3 – FORCE_PHY_ERRSOTHS_3 Force Start of Transmission Error on Data Lane 3 (no synchronization achieved) Interrupt

Bit 2 – FORCE_PHY_ERRSOTHS_2 Force Start of Transmission Error on Data Lane 2 (no synchronization achieved) Interrupt

Bit 1 – FORCE_PHY_ERRSOTHS_1 Force Start of Transmission Error on Data Lane 1 (no synchronization achieved) Interrupt

Bit 0 – FORCE_PHY_ERRSOTHS_0 Force Start of Transmission Error on Data Lane 0 (no synchronization achieved) Interrupt