39.4.8 Analog-to-Digital Converter (ADC) Conversion Timing Specifications

Table 39-14.
Standard Operating Conditions (unless otherwise stated)
Param No.	Sym.	Characteristic	Min.	Typ. †	Max.	Units	Conditions
AD20	T_AD	ADC Clock Period	0.5	—	9	μs	Using F_OSC as the ADC clock source ADCS = `1`
AD21	T_AD	ADC Clock Period	—	2	—	μs	Using F_RC as the ADC clock source ADCS = `0`
AD22	T_CNV	Conversion Time⁽¹⁾	—	14T_AD+2T_CY	—	—	Using F_OSC as the ADC clock source ADCS = 1
AD22	T_CNV	Conversion Time⁽¹⁾	—	16T_AD+2T_CY	—	—	Using F_RC as the ADC clock source ADCS = `0`
AD23	T_ACQ	Acquisition Time	—	2	—	μs
AD24	T_HCD	Sample and Hold Capacitor Disconnect Time	—	2T_AD+1T_CY	—	—	Using F_OSC as the ADC clock source ADCS = 1
AD24	T_HCD	Sample and Hold Capacitor Disconnect Time	—	3T_AD+2T_CY	—	—	Using F_RC as the ADC clock source ADCS = `0`
* - These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: Does not apply for the F_RC oscillator.

Figure 39-10. ADC Conversion Timing (ADC Clock F_OSC-Based)

Figure 39-11. ADC Conversion Timing (ADC Clock from F_RC)

Note:

If the ADC clock source is selected as F_RC, a time of T_CY is added before the ADC clock starts. This allows the SLEEP instruction to be executed.