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Libero IDE v9.x
Libero IDE v9.x
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  2. 13 Libero IDE
  3. 13.25 Device Selection
  4. 13.25.14 Setting Compile Options
  5. 13.25.14.1 Compile Options
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  • 1 FlashROM, Analog System Builder, and Flash Memory System Builder
  • 2 Analog System Builder, FlashROM and Flash Memory System Builder
  • 3 ChipEditor
  • 4 Designer Documentation Catalog
  • 5 Libero IDE
  • 6 Design Constraints for Software
  • 7 Innoveda eProduct Designer Interface Guide - UNIX
  • 8 Innoveda eProduct Designer Interface Guide – Windows
  • 9 FlashPro for Software
  • 10 SmartGen Cores Reference
  • 11 HDL Coding Style
  • 12 Libero IDE Documentation Catalog
  • 13 Libero IDE
    • 13 What's New in Libero IDE v9.1
    • 13.1 Supported Families
    • 13.2 Project Management
    • 13.3 Project Files
    • 13.4 Project Options
    • 13.5 Settings
    • 13.6 Preferences
    • 13.7 Project Manager Interface
    • 13.8 Designing with Designer Block Components
    • 13.9 Creating a Designer Block Component in Libero IDE
    • 13.10 Creating a Designer Block Component in Designer
    • 13.11 Instantiating a Designer Block Component in Designer
    • 13.12 SmartDesign
    • 13.13 Getting Started with SmartDesign
    • 13.14 SmartDesign User Interface
    • 13.15 Canvas View
    • 13.16 Grid
    • 13.17 Instance-Instance View
    • 13.18 Schematic View
    • 13.19 Creating a SmartDesign
    • 13.20 Connecting Instances
    • 13.21 Bus Interfaces
    • 13.22 Incremental Design
    • 13.23 Reference
    • 13.24 Welcome to Designer
    • 13.25 Device Selection
      • 13.25.1 Device Selection Wizard
      • 13.25.2 Setting Die, Package, Speed, and Voltage
      • 13.25.3 Device Variations
      • 13.25.4 Setting Operating Conditions
      • 13.25.5 Changing Design name and family
      • 13.25.6 Changing Device Information
      • 13.25.7 Importing Source Files
      • 13.25.8 Importing Source Files – Copying Files Locally
      • 13.25.9 Auditing Files
      • 13.25.10 Importing Auxiliary Files
      • 13.25.11 Merge SDC File(s) with Existing Timing Constraints
      • 13.25.12 Merge PDC file(s) with existing physical constraints
      • 13.25.13 Compiling your Design
      • 13.25.14 Setting Compile Options
        • 13.25.14.1 Compile Options
      • 13.25.15 IGLOO, ProASIC3, SmartFusion, and Fusion Compile Options
      • 13.25.16 ProASIC and ProASICPLUS Compile Options
      • 13.25.17 Axcelerator Compile Options
      • 13.25.18 MX, SX, SX-A, eX Compile Options
    • 13.26 Design Constraints
    • 13.27 Families Supported
    • 13.28 Entering Constraints
    • 13.29 Running Layout
    • 13.30 Device Programming
    • 13.31 Generating Programming Files
    • 13.32 TCL Command Reference
    • 13.33 Project Manager Tcl Commands
    • 13.34 Reference
    • 13.35 Dialog Boxes
    • 13.36 Revision History
    • 13 Microchip FPGA Support
    • 13 Microchip Information
  • 14 Antifuse Macro Library Guide for Software
  • 15 MultiView Navigator
  • 16 NetlistViewer (non-MVN)
  • 17 IGLOO, ProASIC3, SmartFusion and Fusion Macro Library for Software
  • 18 ProASIC and ProASIC PLUS Macro Library for Software
  • 19 PinEditor (non-MVN)
  • 20 SmartPower
  • 21 SmartTime
  • 22 Timer
  • 23 VHDL Vital Simulation
  • 24 Verilog Simulation
  • 25 Technical Support
  • 26 About Microchip

13.25.14.1 Compile Options

Compile Options vary according to family.
  • IGLOO, Fusion, and ProASIC3
  • ProASIC, ProASICPLUS
  • Axcelerator
  • MX, SX, SX-A, and eX

Rev: A

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