17.7.2 Flash Memory Block Macro

Flash Memory Block

Flash Memory Block is available across the Fusion device family.

Function: Flash memory block builder for use with SmartGen and Fusion.
Inputs/Outputs: See the description as follows for an explanation of the inputs and outputs available on the Flash memory block macro.

Each Flash Memory block holds 256 kb of data. Although it is functionally similar to a large single-port synchronous RAM, it has several significant differences, including:

Address bits are MSB justified, unlike RAM4K9 and RAM512X18 in which the address bits are LSB justi-fied.
Write operation updates write data into the block buffer ONLY. To store data permanently into the Flash Memory Block array writes to a page must be followed by a program operation of the same page.
The simulation models always execute copy page from Flash memory block array (internal operation) in 65 clock cycles; in silicon the behavior is non-deterministic (63-67 clock cycles). This mismatch is reflected in the number of cycles BUSY is asserted.

Operations on Flash memory block are synchronous to rising-edge of CLK.

Flash Memory Block Pin Description

All Flash memory block signals are active high, except for RESET which is active low. The Flash memory block is a completely synchronous model sensitive to rising edge of CLK input.


NAME	FUNCTION
ADDR[17:0]	Byte-offset into the Flash memory block array or block buffer of page buffer
WD[31:0]	Write data
DATAWIDTH[31:0]	00 = 1-byte in data_in/out[7:0] 01 = 2-bytes in data_in/out[15:0] 10/11 = 4-bytes in data_in/out[31:0]
REN	When asserted, initiates a read operation
READNEXT	When asserted with REN, initiates a read from next address after read to current address is complete.
PAGESTATUS	When asserted with read, initiates a read page status operation
WEN	When asserted, interface data is stored into the assembly buffer.
ERASEPAGE	When asserted, erase addressed page (program all zeroes).
PROGRAM	When asserted, write the contents of the assembly buffer into the cell array page addressed.
SPAREPAGE	When asserted, the sector addressed is used to access the spare page within that sector.
AUXBLOCK	When asserted, the page addressed is used to access the auxiliary block within that page.
UNPROTECTPAGE	When asserted, the page addressed is copied into the AB and the AB made writeable.
OVERWRITEPAGE	When asserted, the page addressed is overwritten with the contents of the AB if the page is writeable.
DISCARDPAGE	When asserted, the contents of the AB are discarded so that a new page write can be started.
OVERWRITEPROTECT	When asserted, all program operations set the overwrite protect bit in the auxiliary block of the page being programmed.
PAGELOSSPROTECT	When asserted, a modified assembly buffer must be programmed or discarded before accessing a new page.
PIPE	When asserted with REN, read operation completes in 6 cycles. Required to be asserted for CLK speeds above 50MHz.
LOCKREQUEST	Request to lock user access to Flash memory block array.
CLK	Input clock. All operations and status are synchronous to rising-edge of this clock.
RESET	When asserted resets the state of the Flash memory block.
RD[31:0]	Read data to be sampled when BUSY=0.
STATUS[1:0]	Status of the last operation completed: 00 = successful completion 01 = Read: single error detected and corrected Write: operation addressed a write-protected page Erase-Page/Program: AB is unmodified 10 = Read: two or more errors detected Erase-Page/Program: Compare operation failed 11 = Write: attempt to write to another page before programming current page.

Simulation Details for Flash Memory Block

The Flash memory block array can be pre-loaded with user-defined data. For simulation purposes, you can specify a memory initialization file by over-riding the parameter MEMORYFILE in the verilog netlist and the generic MEMORYFILE in vital netlist.

The memory array declared in simulation models stores data that is one block wide. It is 64k x 140 bits. The addressing scheme for accessing this array consists of 16 bits, as shown in the following figure.

Figure 17-195. Addressing Scheme for Accessing the Flash Memory Block Memory Array

ADDR[17:0] is the Flash memory block interface address, SPAREPAGE and AUXBLOCK are input signals.

The memory file for pre-loading a Flash memory block array consists of "strings of address and data in hexadecimal notation with address delimiters (@)" and MUST conform to the following rules:

Each line MUST contain a string of fixed length (=35 characters) and start with an "@" if it corresponds to an address.
Each line following the address line corresponds to a block of data starting at the block address specified in the address line. This applies until the next line with an address specifier (@) is encountered.
Each data block consists of 35 hex characters. Hex[31:0] are the data characters corresponding to 16 bytes of user data with Hex[1:0] corresponding to Byte0 and Hex[31:30] corresponding to Byte15. Hex[34:32] are ECC related bits and must be addressed manually.

Based on these rules, the format looks like:

@Block_Address_0
Block_Data_0 ( required )
Block_Data_1 ( optional )
Block_Data_2 ( optional )
...
...
Block_Data_8 ( Aux block data for this page, optional )
@Block_Address_n
Block_Data_n ( required )
Block_Data_n+1 ( optional )
Block_Data_n+2 ( optional )
...
...
...
Block_Data_n+8 ( Aux block data for this page, optional )

A typical memory file looks like:

@000…0000 // beginning with @, start address in hex. format. 0s to be padded
// between @ and hex address, to get a string of length 35.
ab101fd01… // 35 hexadecimal characters corresponding to each block of Flash memory
block cell
eab9c4……
@000…4030 // start address for next data stream
c805489e…. // 35 hexadecimal characters corresponding to each block of Flash memory
block cell
96986391…

User Controlled Generics

FAST_SIM: The generic/parameter FAST_SIM is included in pre-synthesis and pre-layout simulation models to reduce cycles wasted in executing the PROGRAM operation. The default is '1', which means the PROGRAM operation is executed with a 4μs simulated delay. You can choose to deactivate the operation by overriding FAST_SIM to 0, in which case PROGRAM is executed with a delay close to the real time of 8.4 ms. You can also choose this mode for post-layout simulations.
WR_THR: When the number of writes to a page in the Flash memory block array (program operation) exceeds the write threshold specified in the data sheet, the status returned is non-zero. Since the threshold is a huge value, WR_THR is provided to simulate this failure at a reduced number of writes. You can override the generic with any non-zero count (such as 10 or 12). The write-threshold-exceeded condition is produced on the 10th write to the same page in the Flash memory block array.

Note: The string assigned to the generic/parameter MEMORYFILE is preserved through synthesis and place-and-route. But for FAST_SIM and WR_THR generics/parameters, you must reassign the desired value each time after synthesis and place-and-route.