17.7.4 Voltage Regulator and Power Supply Monitor Macro
Voltage Regulator and Power Supply Monitor (VRPSM)
Voltage Regulator and Power Supply Monitor (VRPSM) is available across the Fusion device family.
- Function: The Voltage Regulator and Power Supply Monitor were combined into one macro because the VR and power supply logic work together to control the power-up state of the FPGA core.
- Inputs/Outputs: Inputs are listed on the left, outputs on the right. For an explanation of the inputs and outputs, see the VRPSM Signal Description and Power-Up Sequences section.
The VR generates a 1.5 V power supply (500 mA max) from the 3.3 V power supply. The 1.5 V output is intended to supply all 1.5 V needs of the Fusion product. This regulator requires an external bipolar pass transistor. Enable for this block is generated in the VR logic block, or from an external pad.
The 1.5 V is not supplied internally to the Fusion device. It must be routed externally to the VCC pins on the device. Therefore the user is not required to use the V-Reg and can use an off-chip 1.5 V supply if desired.
The VRPSM can be enabled from several sources: the PUB pin, RTCMATCH signal from the Analog Block's RTC, or triggered by the PUP0 (RTINIT1 and RTINIT1, PC bits). In the simulation library, PUP0 is represented by VRINITSTATE. VRINITSTATE is FPGAGOOD initial power-up value. It enables you to drive FPGAGOOD to '1' or '0', before the 3.3V is up. The PUCORE output is the Power-Up Bar (PUB) input inverted.
Once triggered the VRPSM remains on because of the latching functions of RS flip-flops. Only the FPGA fabric can reset these flip-flops and turn off the VRPSM. Once the FPGAGOOD signal is established, this VRPSM enable mechanism is no longer active. For signal descriptions and recommended power-up sequences see the following tables.
VRPSM Signal Description and Power-Up Sequences
The signals for the VPRSM macro are listed in the following table. The PUB input comes from the PUB pin on the device and can be pulled high by a signal external to the Fusion device. This can be used to wake up from a standby condition. The inputs VRINITSTATE and RTCPSMMTACH come from the VR Init and RTC blocks respectively and either can initiate a VR power up.
| NAME | Number of Bits | Direction | FUNCTION |
|---|---|---|---|
| PUB | 1 | INPUT | Power-up bar |
| VRPU | 1 | INPUT | Voltage regulator power-up |
| VRINITSTATE | 1 | INPUT | FPGAGOOD initial value (set by 2 flash bits in the FPGA) |
| RTCPSMMATCH | 1 | INPUT | Connected to RTCMATCH signal from RTC |
| FPGAGOOD | 1 | OUTPUT | Indicates that the FPGA is logically functional |
| PUCORE | 1 | OUTPUT | Power-up to core |
Recommended power up sequences are listed as follows. ? indicates a don’t care value.
| PUB | VRINITSTATE | VRPU | RTCPSMMATCH | FPGAGOOD | |
| Initial power-up | ? | 1 | ? | ? | 1 |
| ? | 0 | ? | ? | 0 | |
| Sequence | 1 | ? | 0 | 0 | 0 |
| 0 | ? | 0 | 0 | 1 | |
| 1 | ? | 1 | 0 | 1 | |
| 1 | ? | 0 | 0 | 0 | |
| Sequence | 1 | ? | 0 | 0 | 0 |
| 1 | ? | 0 | 1 | 1 | |
| 1 | ? | 1 | 0 | 1 | |
| 1 | ? | 0 | 0 | 0 |