17.7.1 RAM and FIFO Macros

RAM4K9 and RAM512X18

There are two RAM macros in the ProASIC3/ProASIC3E library: RAM4K9 and RAM512X18. The RAM4K9 is a fully synchronous, true dual-port RAM with an optional pipeline stage. It can be used for word widths up to 9 bits. Both ports are capable of reading and writing, making it possible to write with both ports or read with both ports simultaneously. You can also read from one port while writing to the other. Each port also has an optional pipeline stage that can be controlled separately via the PIPE pins. The RAM512X18 is a fully synchronous, two-port RAM with an optional pipeline stage. You can use it for word widths of 9 or 18 bits. It has one dedicated read port and one dedicated write port (you can read from one port while writing to the other). The read port also has an optional pipeline stage that you can control separately via the PIPE pin.

During the write operation of the RAM4K9, the WMODE pins control the data that appears on the read pins of the same port. When WMODE is high, the same data appears on the read and write ports at the rising CLK edge. When WMODE is low, the old data stored in the current memory location being addressed appears on the read port. There are no WMODE pins on the RAM512X18.

The aspect ratio of each port can be specified independently via the WIDTHA and WIDTHB pins. For the RAM512X18, the allowable values are 18 x 256 and 9 x 512. For the RAM4K9, the allowable values are 9 x 512, 4 x 1K, 2 x 2K and 1 x 4K. Although it is possible to dynamically reconfigure the aspect ratios, the RAM was designed with only static configuration in mind, so the timing is unknown and you are discouraged from performing such operations. The same is true for the WMODE and PIPE configuration pins.

RAM4K9 and RAM512X18 are available across the IGLOO®, ProASIC3, SmartFusion®, Fusion device families.

• Function: RAM4K9 is a fully synchronous, true dual-port RAM with an optional pipeline stage; RAM512X18 is a fully synchronous, two-port RAM with an optional pipeline stage.
• Input: Inputs are shown on the left of the diagrams. For example, ADDRA11, ADDRA10, ... , ADDRA0.
• Output: Outputs are shown at the right on the diagrams. For example, DOUTA8, DOUT7, ... , DOUT0.

The RAM4K9 only needs 2 bits to configure the WIDTH. The allowable RAM4K9 WIDTHA and WIDTHB values are shown in the following table.

The RAM512X18 also needs 2 bits to configure the read and write widths. The allowable RAM512X18 WW and RW values are shown in the following table.

When specifying a width that is less than the maximum (e.g. 1), the upper unused data input pins (e.g. DINA8 - DINA1) must be connected to GND. When specifying a depth that is less than the maximum (e.g. 512), the upper unused address pins (e.g. ADDRA11 - ADDRA9) must also be connected to GND.

When widths of 1, 2 and 4 are used, the ninth bit is skipped. This can cause counter-intuitive effects when these widths are used for read operations and larger widths are used for write operations (or vice versa). For example, if a width of 9 is used for writing and a width of 1 for reading, every 9th bit is dropped. This effect may be desirable for removing parity bits. If a write width of 4 and read width of 9 is used, the 9th bit may either contain garbage or remnants of previous write operations when a write width of 9 or higher was being used. For this reason, SmartGen only supports the following aspect ratio combinations when one of the ports is configured with a 1-, 2- or 4-bit width using the RAM4K9.

The RAM4K9 can still be used for 9-bit width applications, but no other bit-width can be used with it other than 9-bits.

There are several restrictions that apply when you use an 18 x 256 aspect ratio. For this reason, SmartGen uses the RAM512X18 whenever 18-bit widths are specified. The only allowable combinations of read and write configurations for the RAM512X18 are as follows:

The RADDR pins are always used for the read address in the above configurations and the WADDR pins are used for the write address. The RW pin is used to specify the read width and the WW pin for the write width. The WD pins are used for writing data and the RD pins for reading data.

When deserted, the BLK pins cause the DO outputs to hold their last value. When asserted, the WEN pins can be used to switch each port between write and read mode. The RESET pin sets all outputs low but does not reset the memory. The WMODE pins are used to either allow the write data to appear immediately on the output pins or to hold the last value.

Use SmartGen to configure the RAM for typical use. SmartGen does not support dynamic reconfiguration or cascading width-wise. Customers who wish to use such features must instantiate and configure the RAM macro manually. You can configure your RAM dynamically if you use the FlexRAM macros in the next section.

FLEXRAM4K9 and FLEXRAM512X18

There are two dynamically reconfigurable RAM macros in the Fusion library: FLEXRAM4K9 and FLEXRAM512X18. The FLEXRAM4K9 is a fully synchronous, true dual-port RAM with an optional pipeline stage. It can be used for word widths up to 9 bits. Both ports are capable of reading and writing, making it possible to write with both ports or read with both ports simultaneously. You can also read from one port while writing to the other. Each port also has an optional pipeline stage that can be controlled separately via the PIPE pins. The FLEXRAM512X18 is a fully synchronous, two-port RAM with an optional pipeline stage. You can use it for word widths of 9 or 18 bits. It has one dedicated read port and one dedicated write port (you can read from one port while writing to the other). The read port also has an optional pipeline stage that you can control separately via the PIPE pin.

During the write operation of the FLEXRAM4K9, the WMODE pins control the data that appears on the read pins of the same port. When WMODE is high, the same data appears on the read and write ports at the rising CLK edge. When WMODE is low, the old data stored in the current memory location being addressed appears on the read port. There are no WMODE pins on the FLEXRAM512X18.

The aspect ratio of each port can be specified independently via the WIDTHA and WIDTHB pins. For the FLEXRAM512X18, the allowable values are 18 x 256 and 9 x 512. For the FLEXRAM4K9, the allowable values are 9 x 512, 4 x 1K, 2 x 2K and 1 x 4K. Microchip®recommends that you do not change the WMODE and pipe configuration pins dynamically because the timing is unknown.

FLEXRAM4K9 and FLEXRAM512X18 are available across the Fusion device family.

• Function: FLEXRAM4K9 is a fully synchronous, true dual-port RAM with an optional pipeline stage; FLEXRAM512X18 is a fully synchronous, two-port RAM with an optional pipeline stage
• Input: Inputs are shown on the left of the diagrams. For example, ADDRA11, ADDRA10, ... , ADDRA0.
• Output: Outputs are shown at the right on the diagrams. For example, DOUTA8, DOUT7, ... , DOUT0.

The FLEXRAM4K9 only needs 2 bits to configure the WIDTH. The allowable FLEXRAM4K9 WIDTHA and WIDTHB values are shown in the following table.

The FLEXRAM512X18 also needs 2 bits to configure the read and write widths. The allowable FLEXRAM512X18 WW and RW values are shown in the following table.

When specifying a width that is less than the maximum (e.g. 1), the upper unused data input pins (e.g. DINA8 - DINA1) must be connected to GND. When specifying a depth that is less than the maximum (e.g. 512), the lower unused address pins (e.g. ADDRA2 - ADDRA0) must also be connected to GND.

When widths of 1, 2 and 4 are used, the ninth bit is skipped. This can cause counter-intuitive effects when these widths are used for read operations and larger widths are used for write operations (or vice versa). For example, if a width of 9 is used for writing and a width of 1 for reading, every 9th bit is dropped. This effect may be desirable for removing parity bits. If a write width of 4 and read width of 9 is used, the 9th bit may either contain garbage or remnants of previous write operations when a write width of 9 or higher was being used. For this reason, Microchip® recommends that you use only the following aspect ratio combinations when one of the ports is configured with a 1-, 2- or 4-bit width using the FLEXRAM4K9.

The FLEXRAM4K9 can still be used for 9-bit width applications, but no other bit-width can be reliably used with it other than 9-bits.

There are several restrictions that apply when you use an 18 x 256 aspect ratio. For this reason, Microchip® recommends that you use the FLEXRAM512X18 whenever 18-bit widths are specified. The only allowable combinations of read and write configurations for the FLEXRAM512X18 are as follows:

The RADDR pins are always used for the read address in the above configurations and the WADDR pins are used for the write address. The RW pin is used to specify the read width and the WW pin for the write width. The WD pins are used for writing data and the RD pins for reading data.

When deserted, the BLK pins cause the DO outputs to hold their last value. When asserted, the WEN pins can be used to switch each port between write and read mode. The RESET pin sets all outputs low but does not reset the memory. The WMODE pins are used to either allow the write data to appear immediately on the output pins or to hold the last value.

SmartGen does not support FlexRAM macros; you must instantiate and configure the FlexRAM macros manually.

FIFO4K18

FIFO4K18 is available across the IGLOO®, ProASIC3, SmartFusion®, Fusion device families.

• Function: FIFO4K18 is fully synchronous and has its own built-in controller, capable of variable aspect ratios.
• Input: Inputs are shown on the left of the diagram. For example, AEVAL11, AEVAL10, ... , AEVAL0.
• Output: Outputs are shown at the right on the diagram. For example, RD17, RD16, …, RD0.

FIFO4K18 is fully synchronous and has its own built-in controller. Like the RAM, the FIFO can have different write and read aspect ratios that can be configured dynamically. The WW and RW pins are used to specify one of five allowable aspect ratios, as shown in the following table.

The AEVAL and AFVAL pins are used to specify the almost empty and almost full threshold values, respectively. In order to handle different read and write aspect ratios, the values specified by the AEVAL and AFVAL pins are to be interpreted as the address of the last word stored in the FIFO. The FIFO actually contains separate write address (WADDR) and read address (RADDR) counters. These counters calculate the 12-bit memory address that is a function of WW and RW, respectively. WADDR is incremented every time a write operation is performed and RADDR is incremented every time a read operation is performed. Whenever the difference between WADDR and RADDR is greater than or equal to AFVAL, the AFULL output is raised. Likewise, whenever the difference between WADDR and RADDR is less than or equal to AEVAL, the AEMPTY output is raised. Therefore AEVAL and AFVAL must be left-justified for widths greater than one (i.e. unused lsb’s must be grounded).

When the number of words stored in the FIFO reaches the amount specified by AEVAL while reading, the AEMPTY output goes high. Likewise when the number of words stored in the FIFO reaches the amount specified by AFVAL while writing, the AFULL output goes high. The FULL and EMPTY outputs goes high when the FIFO is completely full or empty, respectively.

It should be noted that the internal memory size is 512 X 9. When widths of 1, 2 and 4 are specified, the 9th bit is skipped.

The ESTOP pin is used to stop the read counter from counting any further once the FIFO is empty (i.e. the EMPTY flag goes high). Likewise, the FSTOP pin is used to stop the write counter from counting any further once the FIFO is full (i.e. the FULL flag goes high). These are configuration pins that should not be dynamically reconfigured. SmartGen treats them as static configuration pins and always ties them high.

Independent read and write operations are allowed, however only the read port can be pipelined. Data on the appropriate WD pins are written to the FIFO every rising WCLK edge as long as WEN and WBLK are low. Data is read from the FIFO and output on the appropriate RD pins every rising RCLK edge as long as REN is high and RBLK is low.

The active low RESET pin is used to asynchronously clear the outputs of the FIFO and reset the internal read and write address counters. It sets all the RD pins low, the FULL and AFULL pins low, and the EMPTY and AEMPTY pins high, however the contents of the memory remain unchanged. RESET has priority over RBLK and WBLK.

When instantiating the FIFO4K18, all unused input pins must be connected to GND.