11.2.3.7 Equality Operator

The equality and non-equality operators indicate a true or false output based on whether the two operands are equivalent or not. The following examples infer equality operators.

VHDL

library IEEE;
use IEEE.std_logic_1164.all;
entity equality is
port (
A: in STD_LOGIC_VECTOR (3 downto 0);
B: in STD_LOGIC_VECTOR (3 downto 0);
Q1: out STD_LOGIC;
Q2: out STD_LOGIC
);
end equality;
architecture equality_arch of equality is
begin
process (A, B)
begin
Q1 <= A = B; -- equality
if (A /= B) then -- inequality
Q2 <= '1';
else
Q2 <= '0';
end if;
end process;
end equality_arch;

library IEEE;
use IEEE.std_logic_1164.all;
entity equality is
port (
A: in STD_LOGIC_VECTOR (3 downto 0);
B: in STD_LOGIC_VECTOR (3 downto 0);
Q1: out STD_LOGIC;
Q2: out STD_LOGIC
);
end equality;
architecture equality_arch of equality is
begin
Q1 <= '1' when A = B else '0'; -- equality
Q2 <= '1' when A /= B else '0'; -- inequality
end equality_arch;

Verilog

module equality (A, B, Q1, Q2);
input [3:0] A;
input [3:0] B;
output Q1;
output Q2;
reg Q1, Q2;
always @ (A or B)
begin
Q1 = A == B; //equality
if (A != B) //inequality
Q2 = 1;
else
Q2 = 0;
end
endmodule