11.2.3.3 Decoders

Decoders are used to decode data that has been previously encoded using binary or another type of encoding. The following examples infer a 3-8 line decoder with an enable.

VHDL

library IEEE;
use IEEE.std_logic_1164.all;
entity decode is
port ( Ain : in std_logic_vector (2 downto 0);
En: in std_logic;
Yout : out std_logic_vector (7 downto 0));
end decode;
architecture decode_arch of decode is
begin
process (Ain)
begin
if (En='0') then
Yout <= (others => '0');
else
case Ain is
when "000" => Yout <= "00000001";
when "001" => Yout <= "00000010";
when "010" => Yout <= "00000100";
when "011" => Yout <= "00001000";
when "100" => Yout <= "00010000";
when "101" => Yout <= "00100000";
when "110" => Yout <= "01000000";
when "111" => Yout <= "10000000";
when others => Yout <= "00000000";
end case;
end if;
end process;
end decode_arch;

Verilog

module decode (Ain, En, Yout);
input En;
input [2:0] Ain;
output [7:0] Yout;
reg [7:0] Yout;
always @ (En or Ain)
begin
if (!En)
Yout = 8'b0;
else
case (Ain)
3'b000 : Yout = 8'b00000001;
3'b001 : Yout = 8'b00000010;
3'b010 : Yout = 8'b00000100;
3'b011 : Yout = 8'b00001000;
3'b100 : Yout = 8'b00010000;
3'b101 : Yout = 8'b00100000;
3'b110 : Yout = 8'b01000000;
3'b111 : Yout = 8'b10000000;
default : Yout = 8'b00000000;
endcase
end
endmodule