An if-then-else statement is used to conditionally execute sequential statements based on
a value. Each condition of the if-then-else statement is checked in order against that
value until a true condition is found. Statements associated with the true condition are
then executed and the rest of the statement is ignored. If-then-else statements should
be used to imply priority on a late arriving signal. In the following examples, shown in
Figure 2-12, signal c is a late arriving signal.Figure 11-13. Priority Encoder Using an
If-Then-Else Statement
VHDL
library IEEE;
use IEEE.std_logic_1164.all;
entity my_if is
port (c, d, e, f: in std_logic;
s : in std_logic_vector(1 downto 0);
pout : out std_logic);
end my_if;
architecture my_arc of my_if is
begin
myif_pro: process (s, c, d, e, f) begin
if s = “00” then
pout <= c;
elsif s = “01” then
pout <= d;
elsif s = “10” then
pout <= e;
else pout <= f;
end if;
end process myif_pro;
end my_arc;
Verilog
module IF_MUX (c, d, e, f, s, pout);
input c, d, e, f;
input [1:0]s;
output pout;
reg pout;
always @(c or d or e or f or s) begin
if (s == 2'b00)
pout = c;
else if (s ==2'b01)
pout = d;
else if (s ==2'b10)
pout = e;
else pout = f;
end
endmodule
