11.2.3.5 Arithmetic Operators

Synthesis tools generally are able to infer arithmetic operators for the target technology. The following examples infer addition, subtraction, division and multiplication operators.

VHDL

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity arithmetic is
port (A, B: in std_logic_vector(3 downto 0);
Q1: out std_logic_vector(4 downto 0);
Q2, Q3: out std_logic_vector(3 downto 0);
Q4: out std_logic_vector(7 downto 0));
end arithmetic;
architecture behav of arithmetic is
begin
process (A, B)
begin
Q1 <= ('0' & A) + ('0' & B); --addition
Q2 <= A - B; --subtraction
Q3 <= A / B; --division
Q4 <= A * B; --multiplication
end process;
end behav;

If the multiply and divide operands are powers of 2, replace them with shift registers. Shift registers provide speed optimized implementations with large savings in area. For example:

Q <= C/16 + C*4;

can be represented as:

Q <= shr (C, “100”) + shl (C, “10”);

or

VHDL Q <= “0000” & C (8 downto 4) + C (6 downto 0) & ”00”;

The functions “shr” and “shl” are available in the IEEE.std_logic_arith.all library.

Verilog
module arithmetic (A, B, Q1, Q2, Q3, Q4);
input [3:0] A, B;
output [4:0] Q1;
output [3:0] Q2, Q3;
output [7:0] Q4;
reg [4:0] Q1;
reg [3:0] Q2, Q3;
reg [7:0] Q4;
always @ (A or B)
begin
Q1 = A + B; //addition
Q2 = A - B; //subtraction
Q3 = A / 2; //division
Q4 = A * B; //multiplication
end
endmodule

If the multiply and divide operands are powers of 2, replace them with shift registers. Shift registers provide speed optimized implementations with large savings in area. For example:

Q = C/16 + C*4;

can be represented as:

Q = {4b'0000 C[8:4]} + {C[6:0] 2b'00};