13.13.9 Convert CoreConsole Components

Your project contains components that were created by CoreConsole. CoreConsole is being replaced by SmartDesign, which incorporates the same functionality with enhanced features.

Microchip recommends that you upgrade and convert your design.

The converted SmartDesign and/or IP Component is fully equivalent in terms of peripheral configuration and connectivity. In addition, your instance, port, and net names are preserved.

When you transition to SmartDesign, your CoreConsole design is converted to a SmartDesign and opened on the SmartDesign Canvas. You must regenerate your SmartDesign component after you transition from CoreConsole.

Converting your component requires a re-synthesis of your design. If you have already completed your design and validation phase and are satisfied with your design then you can choose to continue using CoreConsole.

In SmartDesign you can drag configured cores onto the Canvas where they are viewed as blocks in a functional block diagram. From the Canvas you can:

  • Make connections between your blocks
  • Easily instantiate and connect HDL, Design Block (non-IP Catalog cores), and Microchip macros
  • View individual connection details
  • Show or hide individual nets
  • Set or clear attributes (such as Invert, Tie Low, Tie High, or Tie Open)
  • Add slices
  • Move, duplicate, or delete blocks
  • Add notations such as labels, shapes, lines, or arrows to document your design
  • Auto-stitching interfaces and other connections (such as AMBA)
  • Memory Map / Datasheet - The datasheet reports the memory map of the different subsystems of your design, where a subsystem is any independent bus structure with a Master and Slave peripheral attached.

In certain situations, conversion may not produce a fully equivalent design. In this case, the following message appears in the log window:

Warning: A bus interface ‘<bus interface>’ was found at the top level of component ‘<design>’, the converted design may have different top level ports related to this bus interface. Please check your converted design.

This occurs because CoreConsole and SmartDesign have different rules when connecting bus interfaces to the top level. The design is still functionally the same, except it may have differently named ports related to that bus interface and you may have extra ports related to that bus interface. The extra ports are due to the fact that SmartDesign creates unique output ports in the bus interface even if they are connected to the same pin internally.

See the SmartDesign FAQ for more information on basic operations in CoreConsole and their SmartDesign equivalent. SmartDesign also has specific support for working with processor-based designs.