24.4.6.2 Plus Switches

Table below defines and gives usage examples of Verilog plus switches.


Switch	Definition
+libext+	Used with -y switch.
+delay_mode_path	Specifies the path delay model for simulation.
+delay_mode_unit	Specifies the unit delay model for simulation.
+delay_mode_zero	Functional simulation option; specifies the zero delay model for simulation.
+mindelays	Back-annotation option; selects minimum delay for simulation.
+maxdelays	Back-annotation option; selects maximum delay for simulation.
+typdelays	Back-annotation option; selects typical delay for simulation.
+transport_int_dela ys	Considers the interconnect delays as transport delays instead of inertial; needed with Axcelerator , IGLOO/e, and ProASIC3/E libraries.