14.10 Memory Macros

RAM4FA

This component is supported by 3200DX, MX families.

Function: 64X4 dual-port RAM with falling Write clock and asynchronous Read
Input: RDAD5, RDAD4, RDAD3, RDAD2, RDAD1, RDAD0, WD3, WD2, WD1, WD0, WRAD5, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK
Output: RD3, RD2, RD1, RD0

Table 14-750. Truth Table
WCLK	BLKEN	WEN	Action
↓	BLKENS	1	WD written to WRAD
0	X	X	none
1	X	X	none
X	!BLKENS	X	none
X	X	0	none

Note: RDAD contents always appear at RD.

Note: BLKENS must be driven by a GND or VCC macro.

Note: The use of ACTgen RAM blocks is recommended over direct use of RAM macros because ACTgen includes buffering to achieve optimal performance.

Table 14-751. Modules
Family	RAM
All listed	1

RAM4FF

This component is supported by 3200DX, MX families.

Function: 64X4 dual-port RAM with falling Write clock and falling Read clock
Input: RDAD5, RDAD4, RDAD3, RDAD2, RDAD1, RDAD0, REN, RCLK, WD3, WD2, WD1, WD0, WRAD5, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK
Output: RD3, RD2, RD1, RD0

Table 14-752. Write Truth Table
WCLK	BLKEN	WEN	Action
↓	BLKENS	1	WD written to WRAD
0	X	X	none
1	X	X	none
X	!BLKENS	X	none
X	X	0	none

Table 14-753. Read Truth Table
RCLK	REN	Action
↓	1	RDAD contents appear at RD
0	X	RD is unchanged
1	X	RD is unchanged
X	0	RD is unchanged

Note: BLKENS must be driven by a GND or VCC macro.

Note: The use of ACTgen RAM blocks is recommended over direct use of RAM macros because ACTgen includes buffering to achieve optimal performance.

Table 14-754. Modules
Family	RAM
All listed	1

RAM4FR

This component is supported by 3200DX, MX families.

Function: 64X4 dual-port RAM with falling Write clock and rising Read clock
Input: RDAD5, RDAD4, RDAD3, RDAD2, RDAD1, RDAD0, REN, RCLK, WD3, WD2, WD1, WD0, WRAD5, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK
Output: RD3, RD2, RD1, RD0

Table 14-755. Write Truth Table
WCLK	BLKEN	WEN	Action
↓	BLKENS	1	WD written to WRAD
0	X	X	none
1	X	X	none
X	!BLKENS	X	none
X	X	0	none

Table 14-756. Read Truth Table
RCLK	REN	Action
↑	1	RDAD contents appear at RD
0	X	RD is unchanged
1	X	RD is unchanged
X	0	RD is unchanged

Note: BLKENS must be driven by a GND or VCC macro.

Note: The use of ACTgen RAM blocks is recommended over direct use of RAM macros because ACTgen includes buffering to achieve optimal performance.

Table 14-757. Modules
Family	RAM
All listed	1

RAM4RA

This component is supported by 3200DX, MX families.

Function: 64X4 dual-port RAM with rising Write clock and asynchronous Read
Input: RDAD5, RDAD4, RDAD3, RDAD2, RDAD1, RDAD0, WD3, WD2, WD1, WD0, WRAD5, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK
Output: RD3, RD2, RD1, RD0

Table 14-758. Write Truth Table
WCLK	BLKEN	WEN	Action
↑	BLKENS	1	WD written to WRAD
0	X	X	none
1	X	X	none
X	!BLKENS	X	none
X	X	0	none

Note: RDAD contents always appear at RD.

Note: BLKENS must be driven by a GND or VCC macro.

Note: The use of ACTgen RAM blocks is recommended over direct use of RAM macros because ACTgen includes buffering to achieve optimal performance.

Table 14-759. Modules
Family	RAM
All listed	1

RAM4RF

This component is supported by 3200DX, MX families.

Function: 64X4 dual-port RAM with rising Write clock and falling Read clock
Input: RDAD5, RDAD4, RDAD3, RDAD2, RDAD1, RDAD0, REN, RCLK, WD3, WD2, WD1, WD0, WRAD5, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK
Output: RD3, RD2, RD1, RD0

Table 14-760. Write Truth Table
WCLK	BLKEN	WEN	Action
↑	BLKENS	1	WD written to WRAD
0	X	X	none
1	X	X	none
X	!BLKENS	X	none
X	X	0	none

Table 14-761. Read Truth Table
RCLK	REN	Action
↓	1	RDAD contents appear at RD
0	X	RD is unchanged
1	X	RD is unchanged
X	0	RD is unchanged

Note: BLKENS must be driven by a GND or VCC macro.

Note: The use of ACTgen RAM blocks is recommended over direct use of RAM macros because ACTgen includes buffering to achieve optimal performance.

Table 14-762. Modules
Family	RAM
All listed	1

RAM4RR

This component is supported by 3200DX, MX families.

Function: 64X4 dual-port RAM with rising Write clock and rising Read clock
Input: RDAD5, RDAD4, RDAD3, RDAD2, RDAD1, RDAD0, REN, RCLK, WD3, WD2, WD1, WD0, WRAD5, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK
Output: RD3, RD2, RD1, RD0

Note: Microchip recommends that you do NOT use this macro. Contact Microchip technical support for more information.

Table 14-763. Write Truth Table
WCLK	BLKEN	WEN	Action
↑	BLKENS	1	WD written to WRAD
0	X	X	none
1	X	X	none
X	!BLKENS	X	none
X	X	0	none

Table 14-764. Read Truth Table
RCLK	REN	Action
↑	1	RDAD contents appear at RD
0	X	RD is unchanged
1	X	RD is unchanged
X	0	RD is unchanged

Note: BLKENS must be driven by a GND or VCC macro.

Note: The use of ACTgen RAM blocks is recommended over direct use of RAM macros because ACTgen includes buffering to achieve optimal performance.

Table 14-765. Modules
Family	RAM
All listed	1

RAM8FA

This component is supported by 3200DX, MX families.

Function: 32X8 dual-port RAM with falling Write clock and asynchronous Read
Input: RDAD4, RDAD3, RDAD2, RDAD1, RDAD0, WD7, WD6, WD5, WD4, WD3, WD2, WD1, WD0, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK
Output: RD7, RD6, RD5, RD4, RD3, RD2, RD1, RD0

Table 14-766. Write Truth Table
WCLK	BLKEN	WEN	Action
↓	BLKENS	1	WD written to WRAD
0	X	X	none
1	X	X	none
X	!BLKENS	X	none
X	X	0	none

Note: RDAD contents always appear at RD.

Note: BLKENS must be driven by a GND or VCC macro.

Note: The use of ACTgen RAM blocks is recommended over direct use of RAM macros because ACTgen includes buffering to achieve optimal performance.

Table 14-767. Modules
Family	RAM
All listed	1

RAM8FF

This component is supported by 3200DX, MX families.

Function: 32X8 dual-port RAM with falling Write clock and falling Read clock
Input: RDAD4, RDAD3, RDAD2, RDAD1, RDAD0, REN, RCLK, WD7, WD6, WD5, WD4, WD3, WD2, WD1, WD0, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK
Output: RD7, RD6, RD5, RD4, RD3, RD2, RD1, RD0

Table 14-768. Write Truth Table
WCLK	BLKEN	WEN	Action
↓	BLKENS	1	WD written to WRAD
0	X	X	none
1	X	X	none
X	!BLKENS	X	none
X	X	0	none

Table 14-769. Read Truth Table
RCLK	REN	Action
↓	1	RDAD contents appear at RD
0	X	RD is unchanged
1	X	RD is unchanged
X	0	RD is unchanged

Note: BLKENS must be driven by a GND or VCC macro.

Note: The use of ACTgen RAM blocks is recommended over direct use of RAM macros because ACTgen includes buffering to achieve optimal performance.

Table 14-770. Modules
Family	RAM
All listed	1

RAM8FR

This component is supported by 3200DX, MX families.

Function: 32X8 dual-port RAM with falling Write clock and rising Read clock
Input: RDAD4, RDAD3, RDAD2, RDAD1, RDAD0, REN, RCLK, WD7, WD6, WD5, WD4, WD3, WD2, WD1, WD0, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK
Output: RD7, RD6, RD5, RD4, RD3, RD2, RD1, RD0

Table 14-771. Write Truth Table
WCLK	BLKEN	WEN	Action
↓	BLKENS	1	WD written to WRAD
0	X	X	none
1	X	X	none
X	!BLKENS	X	none
X	X	0	none

Table 14-772. Read Truth Table
RCLK	REN	Action
↑	1	RDAD contents appear at RD
0	X	RD is unchanged
1	X	RD is unchanged
X	0	RD is unchanged

Note: BLKENS must be driven by a GND or VCC macro.

Note: The use of ACTgen RAM blocks is recommended over direct use of RAM macros because ACTgen includes buffering to achieve optimal performance.

Table 14-773. Modules
Family	RAM
All listed	1

RAM8RA

This component is supported by 3200DX, MX families.

Function: 32X8 dual-port RAM with rising Write clock and asynchronous Read
Input: RDAD4, RDAD3, RDAD2, RDAD1, RDAD0, WD7, WD6, WD5, WD4, WD3, WD2, WD1, WD0, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK
Output: RD7, RD6, RD5, RD4, RD3, RD2, RD1, RD0

Table 14-774. Write Truth Table
WCLK	BLKEN	WEN	Action
↑	BLKENS	1	WD written to WRAD
0	X	X	none
1	X	X	none
X	!BLKENS	X	none
X	X	0	none

Note: RDAD contents always appear at RD.

Note: BLKENS must be driven by a GND or VCC macro.

Note: The use of ACTgen RAM blocks is recommended over direct use of RAM macros because ACTgen includes buffering to achieve optimal performance.

Table 14-775. Modules
Family	RAM
All listed	1

RAM8RF

This component is supported by 3200DX, MX families.

Function: 32X8 dual-port RAM with rising Write clock and falling Read clock
Input: RDAD4, RDAD3, RDAD2, RDAD1, RDAD0, REN, RCLK, WD7, WD6, WD5, WD4, WD3, WD2, WD1, WD0, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK
Output: RD7, RD6, RD5, RD4, RD3, RD2, RD1, RD0

Table 14-776. Write Truth Table
WCLK	BLKEN	WEN	Action
↑	BLKENS	1	WD written to WRAD
0	X	X	none
1	X	X	none
X	!BLKENS	X	none
X	X	0	none

Table 14-777. Read Truth Table
RCLK	REN	Action
↓	1	RDAD contents appear at RD
0	X	RD is unchanged
1	X	RD is unchanged
X	0	RD is unchanged

Note: BLKENS must be driven by a GND or VCC macro.

Note: The use of ACTgen RAM blocks is recommended over direct use of RAM macros because ACTgen includes buffering to achieve optimal performance.

Table 14-778. Modules
Family	RAM
All listed	1

RAM8RR

This component is supported by 3200DX, MX families.

Function: 32X8 dual-port RAM with rising Write clock and rising Read clock
Input: RDAD4, RDAD3, RDAD2, RDAD1, RDAD0, REN, RCLK, WD7, WD6, WD5, WD4, WD3, WD2, WD1, WD0, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK
Output: RD7, RD6, RD5, RD4, RD3, RD2, RD1, RD0

Table 14-779. Write Truth Table
WCLK	BLKEN	WEN	Action
↑	BLKENS	1	WD written to WRAD
0	X	X	none
1	X	X	none
X	!BLKENS	X	none
X	X	0	none

Table 14-780. Read Truth Table
RCLK	REN	Action
↑	1	RDAD contents appear at RD
0	X	RD is unchanged
1	X	RD is unchanged
X	0	RD is unchanged

Table 14-781. Modules
Family	RAM
All listed	1

RAM64K36/RAM64K36P

This component is supported by Accelerator families.

Function: Dual port completely independent fully synchronous RAM; the RAM blocks may be cascaded up to 16 by configuring the DEPTH3-0 ports. For RAM64K36P, data appears on RD after 2 clock cycles on RCLK.
Input: RDAD11, ..., RDAD0, WRAD11, ..., WRAD0, WD35, ..., WD0, WEN, REN, WCLK, RCLK, WW2, WW1, WW0, RW2, RW1, RW0, DEPTH3, ..., DEPTH0
Output: RD35, ..., RD0

Note: Microchip recommends you use ACTgen RAM blocks instead of RAM macros because ACTgen configures WW/RW to choose the best aspect ratio and cascades multiple blocks to achieve larger configurations.

Table 14-782. Write Truth Table
WCLK	WEN	Action
1	1	WD written to WRAD
0	1	None
X	0	None

Table 14-783. Read Truth Table
RCLK	REN	Action
1	1	RD is read from RDAD
0	1	RD is unchanged
X	0	RD is unchanged

Table 14-784. Modules
Family	RAM
All listed	1

Table 14-785. SRAM Port Aspect Ratios
Read/Write Depth	Read/Write Depth	Read/Write ADDR Bus	Read/Write Data Bus	RW/WW[2:0]
1	4096	ADDR[11:0]	DATA[0]	000
2	2048	ADDR[10:0]	DATA[1:0]	001
4	1024	ADDR[9:0]	DATA[3:0]	010
9	512	ADDR[8:0]	DATA[8:0]	011
18	256	ADDR[7:0]	DATA[17:0]	100
36	128	ADDR[6:0]	DATA[35:0]	101

FIFO64K36/FIFO64K36P

This component is supported by Accelerator families.

Function: Dual port completely independent fully synchronous FIFO. For FIFO64K36P, data appears on READ after 2 clock cycles on RCLK. FIFO flag behavior is the same as that of FIFO64K36.
Input: WD35, ..., WD0, AFVAL7, ..., AFVAL0, AEVAL7, ..., AEVAL0, WCLK, RCLK, WEN, REN, CLR, WIDTH2, ..., WIDTH0, DEPTH3, ..., DEPTH0
Output: RD35, ..., RD0, FULL, EMPTY, AFULL, AEMPTY

Note: For more information on this macro, see the Accelerator datasheet at Microchip's website.

Table 14-786. Modules
Family	RAM
All listed	1

Table 14-787. FIFO Aspect Ratios Table 1
Data Width	FIFO Depth	Read/Write Data Bus	Width[2:0]
1	4096	DATA[0]	000
2	2048	DATA[1:0]	001
4	1024	DATA[3:0]	010
9	512	DATA[8:0]	011
18	256	DATA[17:0]	100
36	128	DATA[35:0]	101

Table 14-788. FIFO Aspect Ratios Table 2
Depth	Cascaded Blocks	Full	Address Bus WCNT/RCNT	AEVAL/AFVAL Step Size
00001	1	212-W	[15:W]	28-W
00011	2	213-W	[15:W]	28-W
00111	4	214-W	[15:W]	28-W
01111	8	215-W	[15:W]	28-W
11111	16	216-W	[15:W]	28-W

Note: W = width in FIFO Aspect Ratios Table 1.