14.13 PLL Macros

PLL; PLLFB

This component is supported by Accelerator families.

Figure 14-528. PLL and PLLFB Logic Diagram

Function: PLL: PLL with internal feedback; PLLFB: PLL with external feedback
Note: PLL and PLLFB are identical except for the FB pin; if you wish to use internal feedback, use the regular PLL.
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Input: PWRDWN, REFCLK, FB, LOWFREQ, OSC2, OSC1, OSC0, DIV15, DIV14, DIV13, DIV12, DIV11, DIV10, DIVJ5, DIVJ4, DIVJ3, DIVJ2, DIVJ1, DIVJ0, DELAYLINE4, DELAYLINE3, DELAYLINE2, DELAYLINE1, DELAYLINE0
Output: LOCK, CLK1, CLK2

Microchip recommends that you use ACTgen to generate your PLLs; ACTgen calculates the settings for all the pins in the PLL for the required input-output frequency combinations.

For more information, refer to the latest Microchip datasheets on PLLs for Accelerator.

PLLINT

This component is supported by Accelerator families.

Function: PLL Int
Input: A
Output: Y

Table 14-967. Truth Table
A	Y
0	0
1	1

Note: Connect only to the REFCLK input of PLL when the PLL is driven by a pad other than the one in the same super cluster.

For more information, refer to the latest Microchip datasheets on PLLs for Accelerator.

PLLOUT

This component is supported by Accelerator families.

Function: PLL OUT
Input: A
Output: Y

Table 14-968. Truth Table
A	Y
0	0
1	1

Note: Connect only to the CLK output of PLL when the PLL is driving a net other than the HCLK/RCLK networks.

PLLHCLK

This component is supported by Accelerator families.

Function: PLL HCLK
Input: A
Output: Y

Table 14-969. Truth Table
A	Y
0	0
1	1

Note: Connect only to the CLK output of the PLL; use it to drive the HCLK network.

For more information, refer to the latest Microchip datasheets on PLLs for Accelerator.

PLLRCLK

This component is supported by Accelerator families.

Function: PLL RCLK
Input: A
Output: Y

Table 14-970. Truth Table
A	Y
0	0
1	1

Note: Connect only to the CLK output of the PLL; use it to drive the RCLK network.

For more information, refer to the latest Microchip datasheets on PLLs for Accelerator.