14.14 RTAX-DSP Math Macro

MATH18X18

This component is supported by Accelerator families.

Function: 18 bit x 18 bit signed (2’s complement) multiply-accumulate MATH block. The MATH block can accumulate the current multiplication product with a previous result, a constant, a dynamic value, or a result from another MATH block. Each MATH block can also be fractured into two 9 bit x 9 bit multipliers. All the signals of the MATH block, except CIN, CDIN and CDOUT, have optional registers.
Input: CLK[1:0], ARSTAT[1:0], ARSTB[1:0], ARSTP[1:0], SRSTA[1:0], SRSTB[1:0], SRSTP[1:0], EA[1:0], EB[1:0], EP[1:0], ALSHFTSEL, ALCDSEL, ALFDBKSEL, ALSUB, SLSHFTSEL, SLCDSEL, SLFDBKSEL, SLSUB, ESHFTSEL, ECDSEL, EFDBKSEL, ESUB, SHFTSEL, CDSEL, FDBKSEL, SUB, A[17:0], B[17:0], CDIN[40:0], CIN[40:0], ALAT[1:0], BLAT[1:0], PLAT[1:0], SHFTSELLAT, CDSELLAT, FDBKSELLAT, SUBLAT, SIMD, SHFTSELAD, CDSELAD, FDBKSELSD, SUBSD, FDBKSELAD, SUBAD, SHFTSELSD, CDSELSD
Output: P[40:0], CDOUT[40:0], OVFL

Table 14-971. Math18x18 Ports
Port Name	Direction	Type	Polarity	Description
SIMD	Input	Static	High	Single Instruction Multiple Data mode.When SIMD = 1, MATH block is fractured into two 9 bit x 9 bit multipliersWhen SIMD = 0, it is called the normal mode

CLK[1:0]	Input	Dynamic	Rising edge	Input clocks.CLK[1] is the clock for A[17:9], B[17:9], P[40:18], OVFL,SHFTSEL, CDSEL, FDBKSEL and SUB registersCLK[0] is the clock for A[8:0], B[8:0] and P[17:0] In normal mode, ensure CLK[1] = CLK[0]

A[17:0]	Input	Dynamic	High	Input data A
ALAT[1:0]	Input	Static	High	Bypass data A registersALAT[1] is for A[17:9]. Connect to 1, if not registeredALAT[0] is for A[8:0]. Connect to 1, if not registered In normal mode, ensure ALAT[0] = ALAT[1]
ARSTA[1:0]	Input	Dynamic	Low	Asynchronous reset for data A registers.ARSTA[1] is for A[17:9]. Connect to 1, if not registeredARSTA[0] is for A[8:0]. Connect to 1, if not registered In normal mode, ensure ARSTA[1] = ARSTA[0]
SRSTA[1:0]	Input	Dynamic	Low	Synchronous reset for data A registersSRSTA[1] is for A[17:9]. Connect to 1, if not registeredSRSTA[0] is for A[8:0]. Connect to 1, if not registered In normal mode, ensure SRSTA[1] = SRSTA[0]
EA[1:0]	Input	Dynamic	High	Enable for data A registersEA[1] is for A[17:9]. Connect to 1, if not registeredEA[0] is for A[8:0]. Connect to 1, if not registered In normal mode, ensure EA[1] = EA[0]

B[17:0]	Input	Dynamic	High	Input data B
BLAT[1:0]	Input	Static	High	Bypass data B registers.BLAT[1] is for B[17:9]. Connect to 1, if not registered.BLAT[0] is for B[8:0]. Connect to 1, if not registered. In normal mode, ensure BLAT[0] = BLAT[1].
ARSTB[1:0]	Input	Dynamic	Low	Asynchronous reset for data B registers.ARSTB[1] is for B[17:9]. Connect to 1, if not registered.ARSTB[0] is for B[8:0]. Connect to 1, if not registered. In normal mode, ensure ARSTB[1] = ARSTB[0].
SRSTB[1:0]	Input	Dynamic	Low	Synchronous reset for data B registers.SRSTB[1] is for B[17:9]. Connect to 1, if not registered.SRSTB[0] is for B[8:0]. Connect to 1, if not registered. In normal mode, ensure SRSTB[1] = SRSTB[0].
EB[1:0]	Input	Dynamic	High	Enable for data B registers.EB[1] is for B[17:9]. Connect to 1, if not registered.EB[0] is for B[8:0]. Connect to 1, if not registered. In normal mode, ensure EB[1] = EB[0].
P[40:0]	Output		High	Result data.Normal modeP = C + (A × B), when SUB = 0 P = C - (A × B), when SUB = 1SIMD mode PL = AL × BLPH = CH + (AH × BH), when SUB = 0PH = CH - (AH × BH), when SUB = 1Notation:AL = A[8:0], AH = A[17:9]BL = B[8:0], BH = B[17:9]PL = P[17:0], PH = P[40:18] CH = C[40:18].See Table 4 on page 324 to see how operand C is obtained from CIN, Por CDIN.
OVFL	Output		High	Overflow.Normal modeif C +/- (A x B) > (240 ) - 1, then OVFL = 1 if C +/- (A x B) < -(240), then OVFL = 1otherwise, OVFL = 0SIMD modeif CH +/- (AH x BH) > (222) - 1, then OVFL = 1 if CH +/- (AH x BH) < -(222), then OVFL = 1otherwise, OVFL = 0
PLAT[1:0]	Input	Static	High	Bypass result P registers.PLAT[1] is for P[40:18] and OVFL. Connect to 1, if not registeredPLAT[0] is for P[17:0]. Connect to 1, if not registered In normal mode, ensure PLAT[0] = PLAT[1].
ARSTP[1:0]	Input	Dynamic	Low	Asynchronous reset for result P registers.ARSTP[1] is for P[40:18] and OVFL. Connect to 1, if not registered.ARSTP[0] is for P[17:0]. Connect to 1, if not registered In normal mode, ensure ARSTP[1] = ARSTP[0].
SRSTP[1:0]	Input	Dynamic	Low	Synchronous reset for result P registers.SRSTP[1] is for P[40:18] and OVFL. Connect to 1, if not registered.SRSTP[0] is for P[17:0]. Connect to 1, if not registered. In normal mode, ensure SRSTP[1] = SRSTP[0].
EP[1:0]	Input	Dynamic	High	Enable for result P registers.EP[1] is for P[40:18] and OVFL. Connect to 1, if not registered.EP[0] is for P[17:0]. Connect to 1, if not registered. In normal mode, ensure EP[1] = EP[0].

CDOUT[40:0]	Output	Cascade	High	Cascade output of result P.CDOUT is the same as P. The entire bus must either be dangling or drive an entire CDIN of another MATH block in cascaded mode.

CIN[40:0]	Input	Dynamic	High	Routed input for operand C.In SIMD mode, connect CIN[17:0] to 0.See Table 4 on page 324 to see how CIN is propagated to operand C.
CDIN[40:0]	Input	Cascade	High	Cascaded input for operand C.The entire bus must be driven by an entire CDOUT of another MATH block.See Table 4 on page 324 to see how CDIN is propagated to operand C.

SHFTSEL	Input	Dynamic	High	Arithmetic right-shift for operand C.When asserted, a 17-bit arithmetic right-shift is performed on operand C going into the accumulator.In SIMD mode, SHFTSEL is ignored.See Table 4 on page 324 to see how operand C is obtained from CIN, P or CDIN.
SHFTSELLAT	Input	Static	High	Bypass SHFTSEL register. Connect to 1, if not registered.
ALSHFTSEL	Input	Dynamic	Low	Asynchronous load for SHFTSEL register. Connect to 1, if not registered.When asserted, SHFTSEL register is loaded with SHFTSELAD.
SHFTSELAD	Input	Static	High	Asynchronous load data for SHFTSEL register.
SLSHFTSEL	Input	Dynamic	Low	Synchronous load for SHFTSEL register. Connect to 1, if not registered.See Table 2 on page 324
SHFTSELSD	Input	Static	Low	Synchronous load data for SHFTSEL register. See Table 2 on page 324
ESHFTSEL	Input	Dynamic	High	Enable for SHFTSEL register. Connect to 1, if not registered. See Table 2 on page 324

CDSEL	Input	Dynamic	High	Select CDIN for operand C.When CDSEL = 1, propagate CDIN.When CDSEL = 0, propagate CIN or P depending on FDBKSEL. In SIMD mode, CDSEL is ignored for CDIN[17:0] and only CDIN[40:18] is propagated.See Table 4 on page 324 to see how operand C is obtained from CIN, P or CDIN.
CDSELLAT	Input	Static	High	Bypass CDSEL register. Connect to 1, if not registered.
ALCDSEL	Input	Dynamic	Low	Asynchronous load for CDSEL register. Connect to 1, if not registered. When asserted, CDSEL register is loaded with CDSELAD.
CDSELAD	Input	Static	High	Asynchronous load data for CDSEL register.
SLCDSEL	Input	Dynamic	Low	Synchronous load for CDSEL register. Connect to 1, if not registered. See Table 2 on page 324.
CDSELSD	Input	Static	Low	Synchronous load data for CDSEL register. See Table 2 on page 324.
ECDSEL	Input	Dynamic	High	Enable for CDSEL register. Connect to 1, if not registered. See Table 2 on page 324.

FDBKSEL	Input	Dynamic	High	Select the feedback from P for operand C.When FDBKSEL = 1, propagate the current value of result P register. Ensure PLAT[1] = 0 and CDSEL = 0.When FDBKSEL = 0, propagate CIN. Ensure CDSEL = 0. To load P from CIN, ensure either A = 0 or B = 0.In SIMD mode, FDBKSEL is ignored for P[17:0] and only P[40:18] is propagated.See Table 4 on page 324 to see how operand C is obtained from CIN, P or CDIN.
FDBKSELLAT	Input	Static	High	Bypass FDBKSEL register. Connect to 1, if not registered.
ALFDBKSEL	Input	Dynamic	Low	Asynchronous load for FDBKSEL register. Connect to 1, if not registered.When asserted, FDBKSEL register is loaded with FDBKSELAD.
FDBKSELAD	Input	Static	High	Asynchronous load data for FDBKSEL register.
SLFDBKSEL	Input	Dynamic	Low	Synchronous load for FDBKSEL register. Connect to 1, if not registered.See Table 2 on page 324.
FDBKSELSD	Input	Static	Low	Synchronous load data for FDBKSEL register. See Table 2 on page 324.
EFDBKSEL	Input	Dynamic	High	Enable for FDBKSEL register. Connect to 1, if not registered. See Table 2.
SUB	Input	Dynamic	High	Subtract operation.When SUB = 1, perform Two's complement subtraction to get result P= C - (A x B).When SUB = 0, perform Two's complement addition to get result P = C + (A x B).
SUBLAT	Input	Static	High	Bypass SUB register. Connect to 1, if not registered.
ALSUB	Input	Dynamic	Low	Asynchronous load for SUB register. Connect to 1, if not registered. When asserted, SUB register is loaded with SUBAD.
SUBAD	Input	Static	High	Asynchronous load data for SUB register.
SLSUB	Input	Dynamic	Low	Synchronous load for SUB register. Connect to 1, if not registered. See Table 2.
SUBSD	Input	Static	Low	Synchronous load data for SUB register. See Table 2.
ESUB	Input	Dynamic	High	Enable for SUB register. Connect to 1, if not registered. See Table 2.

Table 14-972. Truth Table for Control Registers SHFTSEL, CDSEL, FDBKSEL and SUB
al	ad	lat	clk	en	sl	sd	d	q
0	x	x	x	x	x	x	x	ad
1	x	0	not rising	x	x	x	x	q
1	x	0	rising	0	x	x	x	q
1	x	0	rising	1	0	x	x	!sd
1	x	0	rising	1	1	x	x	d
1	x	1	x	0	x	x	x	q
1	x	1	x	1	0	x	x	!sd
1	x	1	x	1	1	x	x	d

Table 14-973. Truth Table for Data Registers A, B, P and OVFL
arst	lat	clk	en	srst	d	q
0	x	x	x	x	x	0
1	0	not rising	x	x	x	q
1	0	rising	0	x	x	q
1	0	rising	1	0	x	0
1	0	rising	1	1	x	d
1	1	x	0	x	x	q
1	1	x	1	0	x	0
1	1	x	1	1	x	d

Table 14-974. Truth Table for Propagating Data to Operand C
FDBKSEL	CDSEL	SHFTSEL	SIMD	Operand C
0	0	0	0	CIN[40:0]
0	0	x	1	CIN[40:0]

Table 14-975. Truth Table for Propagating Data to Operand C
FDBKSEL	CDSEL	SHFTSEL	SIMD	Operand C
0	0	1	0	{{17{CIN[40]}},CIN[40:17]}
x	1	0	0	CDIN[40:0]
x	1	x	1	{CDIN[40:18],CIN[17:0]}
x	1	1	0	{{17{CDIN[40]}},CDIN[40:17]}
1	0	0	0	P[40:0]
1	0	x	1	{P[40:18],CIN[17:0]}
1	0	1	0	{{17{P[40]}},P[40:17]}