11.4.8.3 Instantiating “CNT5” in the Top Level Design

Once you have created both architectures, instantiate “CNT5” into your design, adding binding statements for both architectures. The binding statements are used to specify which architecture the synthesis tool uses in the design. The technology independent RTL architecture might not meet the performance requirements. The Microchip specific DEF_ARCH architecture is optimized for the Microchip FPGA architecture and may provide higher performance. By removing the comment on one of the “use” statements in the code, a particular architecture can be chosen to meet the design needs.

library IEEE;
use IEEE.std_logic_1164.all;
entity counter is
port (bus_d: in std_logic_vector(4 downto 0);
bus_q: out std_logic_vector(4 downto 0);
net_clock, net_aclr, net_enable: in std_logic;
net_sload: in std_logic);
end counter;
architecture RTL of counter is
-- Component Declaration
component CNT5
port (Data : in std_logic_vector(4 downto 0);Enable, Sload,
Aclr, Clock : in std_logic; Q : out std_logic_vector(4
downto 0));
end component;
-- Binding statements to specify which CNT5 architecture to use
-- RTL architecture for behavioral CNT5
-- DEF_ARCH architecture for structural (SmartGen) CNT5
-- for all: CNT5 use entity work.CNT5(RTL);
-- for all: CNT5 use entity work.CNT5(DEF_ARCH);
begin
-- Concurrent Statement
U0: CNT5 port map (Data => bus_d,
Sload => net_sload,
Enable => net_enable,
Aclr => net_aclr;
Clock => net_clock,
Q => bus_q);
end rtl;