11.4.8.2 Structural Architecture

This implementation of “CNT5” is created by the SmartGen core builder. The port names for the RTL description must match the port names of the structural “CNT5” netlist generated by SmartGen.

library ieee;
use ieee.std_logic_1164.all;
library ACT3;
entity CNT5 is
port (Data : in std_logic_vector(4 downto 0);Enable, Sload,
Aclr, Clock : in std_logic; Q : out std_logic_vector(4
downto 0)) ;
end CNT5;
architecture DEF_ARCH of CNT5 is
component DFM7A
port(D0, D1, D2, D3, S0, S10, S11, CLR, CLK : in
std_logic; Q : out std_logic);
end component;
. . .
end DEF_ARCH;