11.4.8.1 RTL Architecture

This implementation of “CNT5” is written as a behavioral description directly into the design.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity CNT5 is
port (Data: in std_logic_vector(4 downto 0);
Sload, Enable, Aclr, Clock: in std_logic;
Q: out std_logic_vector(4 downto 0));
end CNT5;
architecture RTL of CNT5 is
signal cnt: std_logic_vector(4 downto 0);
begin
counter : process (Aclr, Clock)
begin
if (Aclr = '0') then
cnt <= (others => '0'); -- asynchronous reset
elsif (Clock'event and Clock = '1') then
if (Sload = '1') then
cnt <= Data;-- synchronous load
elsif (Enable = '1') then
cnt <= cnt + '1'; -- increment counter
end if;
end if;
end process;
Q <= cnt; -- assign counter output to output port
end RTL;