Jump to main content

Libero IDE v9.x

Home
13 Libero IDE
13.25 Device Selection
13.25.17 Axcelerator Compile Options
13.25.17.3 Netlist Optimization

Previous | Next

1 FlashROM, Analog System Builder, and Flash Memory System Builder
2 Analog System Builder, FlashROM and Flash Memory System Builder
3 ChipEditor
4 Designer Documentation Catalog
5 Libero IDE
6 Design Constraints for Software
7 Innoveda eProduct Designer Interface Guide - UNIX
8 Innoveda eProduct Designer Interface Guide – Windows
9 FlashPro for Software
10 SmartGen Cores Reference
11 HDL Coding Style
12 Libero IDE Documentation Catalog
13 Libero IDE
14 Antifuse Macro Library Guide for Software
15 MultiView Navigator
16 NetlistViewer (non-MVN)
17 IGLOO, ProASIC3, SmartFusion and Fusion Macro Library for Software
18 ProASIC and ProASIC PLUS Macro Library for Software
19 PinEditor (non-MVN)
20 SmartPower
21 SmartTime
22 Timer
23 VHDL Vital Simulation
24 Verilog Simulation
25 Technical Support
26 About Microchip

13.25.17.3 Netlist Optimization

This interface allows you to perform netlist optimization.

Figure 13-81. Netlist Optimization

Rev: A

About

Company

Careers

Contact Us

Media Center

Investor Relations

Corporate Responsibility

Support

Microchip Forums

AVR Freaks

Design Help

Technical Support

Export Control Data

PCNs

Quick Links

microchipDIRECT.com

Microchip University

myMicrochip

Blogs

Reference Designs

Parametric Search

Microchip Technology Inc.

2355 West Chandler Blvd.

Chandler, Arizona, USA

Microchip Twitter

Microchip Weibo

© Copyright 1998-2024 Microchip Technology Inc. All rights reserved. Shanghai ICP Recordal No.09049794

Terms Of Use

Privacy Notice

Legal

Your Privacy Choices California Consumer Privacy Act (CCPA) Opt-Out Icon

California Consumer Privacy Act (CCPA) Opt-Out Icon