5.23.4.1 Changing memory content

For certain cores such as Analog System Builder, Flash Memory, or FlexRAM it is possible to change the configuration such that only the memory content used for programming is altered. In this case Project Manager (IDE) will only invalidate your programming file, but your synthesis, compile, and place-and-route results will remain valid.

When you modify the memory content of a core such as Analog System Builder or RAM with Initialization that is used by a Flash Memory core, the Flash Memory core indicates that one of its dependent components has changed and

that it needs to be regenerated. This indication will be shown in the Hierarchy or Files Tab .

In these cases, the Project Manager indicates that your programming file is out of date but your synthesis and place-and-route remain valid. You only need to regenerate your programming file in FlashPoint.

If any core is regenerated where the HDL file is not modified, the Project Manager design state will not invalidate your Synthesis and/or Place-and-Route results. Some specific cores are listed below.

RAM with Initialization core - You can modify the memory content without invalidating synthesis.

Analog System Builder core - You can modify the following without invalidating synthesis:

• Existing flag settings: threshold levels, assertion/de-assertion counts, OVER/UNDER type
• Modifying sequence order or adding sequence operations
• Changing acquisition times
• Resistor Value for the Current Monitor

• RTC time settings
• Gate Driver source current

Flash Memory System Builder core - You can modify the following without invalidating synthesis:

• Modifying memory file or memory content for clients
• JTAG protection for Init Clients