5.3.1.3 Step Three - Synthesis/EDIF Generation

Use Synplify Pro ME to generate your EDIF netlist. You can re-verify your design "post-synthesis" using the VHDL or Verilog ModelSim simulator used in step two.

While all RTL code must be synthesized, pure schematic designs are automatically "netlisted" out via the Libero IDE tools to create a structural VHDL or structural Verilog netlist.