5.3.1.2 Step Two - Design Verification - Functional Simulation

After you have defined your design, you must verify that it functions the way you intended. After creating a testbench using WaveFormer Pro, use the ModelSim VHDL or Verilog simulator to perform functional simulation on your schematic or HDL design.

If you have an EDIF netlist created with the full version of ModelSim you can import the netlist into your project and skip directly to Design Implementation (step four).

EDIF Flow Support - You can import an EDIF netlist in Project Manager. If you do not have HDL source files in your project, the EDIF netlist is considered to be a source for the flow.

The name of your block as specified in the EDIF netlist is displayed in the Hierarchy under the work library and is automatically Set as Root. The Project Flow window is updated to show the EDIF flow: synthesis is unavailable and you can go directly to Designer or to Simulation as you would do in the post-synthesis state of the regular HDL flow. If you launch ModelSim, Project Manager automatically creates an HDL netlist.

The Configure Project Flow dialog does not allow you to activate synthesis.

As soon as you import an HDL Source file, the Hierarchy tab does not display the EDIF netlist any more and the Project Flow window is updated to show the regular HDL flow.

Note: If you have a regular HDL project with a synthesized EDIF netlist and remove all the source files from your project, the Project Design Flow will be changed to the EDIF flow and the EDIF netlist will appear in the Design Hierarchy.