8.5.4.2 Design Implementation

During design implementation, use Designer to place-and-route a design. Additionally, you can perform static-timing analysis on a design in Designer with the Timer tool. After place-and-route, perform postlayout (timing) simulation with the Innoveda SpeedWave software.

Place-and-Route

Use Designer to place-and-route your design. Make sure to use GENERIC for the Edif flavor when importing the EDIF netlist into Designer. For information about using Designer, see the Designer On-line Help.

Static-Timing Analysis

Use the Timer tool in Designer to perform static-timing analysis on your design. For information about using Timer, see the Timer On-line Help .

Timing Simulation

Perform a timing simulation of your design after placing-and-routing it. Timing simulation uses information extracted from Designer, which overrides unit delays in the Actel VHDL. See Timing Simulation if using Viewsim or Timing Simulation if using SpeedWave. For information about performing timing simulation, see the Innoveda documentation.