8.5.4.1 Design Creation/Verification
During design creation/verification, a design is captured in an RTL-level (behavioral) VHDL source file. After capture of the design, you may perform a behavioral simulation of the VHDL file with SpeedWave to verify that the VHDL code is correct. The code is then synthesized into a structural EDIF netlist using FPGA Express. After synthesis, you can perform a structural simulation of the design with SpeedWave or ViewSim. Import the EDIF netlist into Designer and perform a timing simulation using SpeedWave or ViewSim.
- VHDL Design Source Entry
- Enter your design source using a text editor or a context-sensitive VHDL editor. Your VHDL design source can contain RTL-level constructs, as well as instantiations of structural elements, such as SmartGen cores.
- Behavioral Simulation
- If SpeedWave is available, perform a behavioral simulation of your design before synthesis. Behavioral simulation verifies the functionality of your VHDL code. Typically, unit delays are used and a standard VHDL test bench can be used to drive simulation. For information about performing behavioral simulation, see Behavioral Simulation and the Innoveda documentation.
- Synthesis
- Synthesize your design using FPGA Express. This transforms the behavioral VHDL file into a gate-level EDIF netlist, optimizing the design for a target technology.
- Structural VHDL Netlist Generation
- If you use SpeedWave for structural and timing simulation, generate a structural VHDL netlist from your EDIF netlist by either exporting it from Designer or by using the Actel “edn2vhdl” program. For information about generating a structural netlist, see Generating a Structural VHDL Netlist.
- Structural Simulation
- Perform a structural simulation of your design before placing-and-routing it. Structural simulation verifies the functionality of your postsynthesis structural netlist. Unit delays are used for each gate. If using ViewSim, see Functional Simulation ,or, if using Speedwave, see Structural Simulation. For information about performing structural simulation, see the Innoveda documentation.