15.2.10 Flash*Freeze Pins

The Flash*Freeze pin is a dedicated pin used to enter or exit Flash*Freeze mode; the pin can also be routed internally to the FPGA core to allow your logic to decide if it is safe to transition to this mode. If you do not use Flash*Freeze technology, you can use the Flash*Freeze pin as a regular I/O to take advantage of the low power consumption of IGLOOe, IGLOO, and ProASIC3L devices.

In PinEditor, the package pin assigned as a Flash*Freeze pin displays "FF/.." preceding the pin name, for example, FF/GEB2/IO108PDC4B0 but only when no I/O sits on the same location.

The Flash*Freeze port is displayed as a locked port in both ChipPlanner and the Hierarchy window's Ports tab. You cannot move or unassign it. The "FF/.." label is not visible in ChipPlanner.

You can assign only one Flash*Freeze pin per IGLOOe, IGLOO, IGLOO PLUS, or ProASIC3L device.

The Flash*Freeze pin is specific to a die-package combination. See the IGLOO and IGLOOe Low Power Flash FPGAs with Flash*Freeze Technology Application Note. For information on which pin to use as the Flash*Freeze pin, see the tables in the Application Note.