2.12.7 EEPromWDTimer eepWdtConf
The sEEPromWDTimer eepWdtConf variable contains the setting for the watchdog timer configuration.
confT0CR
The confT0CR variable is a copy of the timer0 control register (T0CR). The variable is copied to the hardware register during system initialization but not further supported by the firmware. See Timer0 – Watchdog/Interval Timer for a hardware description.
Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|---|---|
0x0091 | confT0CR | — | — | — | T0PR | T0IE | T0PS[2:0] |
Bits 7..5: Reserved Bits
These bits are reserved for future use and must be set to ‘0
’.
Bit 4: T0PR – Timer0 Prescaler Reset
Bit 3: T0IE – Timer0 Interrupt Enable
Bits 2..0: T0PS[2:0] – Timer0 Prescaler Selection
confT0IFR
The confT0IFR variable is a copy of the timer0 interrupt flag register (T0IFR). The variable is copied to the hardware register during system initialization but not further supported by the firmware. See Timer0 – Watchdog/Interval Timer for a hardware description.
Address |
Name |
Bit 7 |
Bit 6 |
Bit 5 |
Bit 4 |
Bit 3 |
Bit 2 |
Bit 1 |
Bit 0 |
---|---|---|---|---|---|---|---|---|---|
0x0092 |
confT0IFR | — | — | — | — | — | — | — |
T0F |
Bits 7..1: Reserved Bits
These bits are reserved for future use and must be set to ‘0
’.
Bit 0: T0F – Timer0 Flag
confWDTCR
The confWDTCR variable is a copy of the watchdog timer control register (WDTCR). See Watchdog Configuration for a functional description, and Timer0 – Watchdog/Interval Timer for a hardware description.
Address |
Name |
Bit 7 |
Bit 6 |
Bit 5 |
Bit 4 |
Bit 3 |
Bit 2 |
Bit 1 |
Bit 0 |
---|---|---|---|---|---|---|---|---|---|
0x0093 |
confWDTCR | — | — | — |
WDCE |
WDE |
WDPS[2:0] |
Bits 7..5: Reserved Bits
These bits are reserved for future use and must be set to ‘0
’.
Bit 4: WDCE – Watchdog Change Enable
This bit is controlled by the firmware and must be set to ‘0
’.
Bit 3: WDE – Watchdog Enable
0
= Watchdog timer disabled
1
= Watchdog timer enabled
Bits 2..0: WDPS[2:0] – Watchdog Timer Prescaler Selection
The WDPS value determines the watchdog time-out period.
WDPS[2:0] |
Timeout at VCC = 3V/25°C | |||
---|---|---|---|---|
Typical |
Minimum | |||
|
|
|
1 ms |
0.85 ms |
|
|
|
4 ms |
3.4 ms |
|
|
|
32 ms |
27 ms |
|
|
|
2.1s |
1.75s |
|
|
|
4.2s |
3.5s |
|
|
|
16.8s |
14s |
|
|
|
134s |
110s |
|
|
|
268s |
220s |